By Pete Singer, Editor-in-Chief
Although the Xpedition was announced last week, it has been used in production for over two years. says five companies have been using it, two of which are extremely large semiconductor companies. “It’s a pretty mature technology,” he said.
Traditionally, chip, package and board designers have used relatively archaic means of communicating, including spreadsheets, whiteboard drawings and Microsoft’s VISIO (a diagramming and vector graphics application). Each group often uses different naming conventions as well, which further complicates co-design efforts.
“They try to use non-EDA technology to figure out an EDA problem,” said John Park, Methodology Architect, Systems Design Division at Mentor Graphics (Longmont, CO).
A new product from Mentor Graphics called Xpedition® Package Integrator provides a new methodology and platform in addition to a new suite of EDA tools. The platform enables chip, package and board designers to easily see how changing various design elements impact adjacent designs, an industry first.
Xpedition allows designers to pull in existing data in whatever form they’re presently using and examine different design considerations such as connectivity across all three design domains. “We’re aggregating people’s existing flow. We’re not replacing them,” Park said.
Park said the development of Xpedition was driven by the general need to simplify co-design, but also to address news challenges created by the Internet of Things (IoT) and new technology such as 2.5 and 3D integration and through-silicon-vias (TSVs). “You’re talking fairly sophis- ticated connectivity management when dealing with multiple die, the interposer and modeling that connec- tivity all the way up to the boards,” Park said. “It’s a pretty challenging problem for most people who have historically tried to use spreadsheets to manage that cross-domain connectivity.”
The Xpedition Package Integrator product also provides the industry’s first formal flow for ball grid array (BGA) ball-map planning and optimization based on an “intelligent pin” concept, defined by user rules. In addition, a new multi-mode connectivity management system (incorporating hardware description language (HDL), spreadsheet and graphical schematic) provides cross-domain pin-mapping and system level cross-domain logical verification (FIGURE 1).
A modern day CPU or GPU has three of four packaging options, such as package-on-package, micro-BGA, or package-on-package (PiP). People are also targeting multiple end form factors. “It’s not a single board anymore,” Park said. “A lot of customers want to look at the device in the context of smartphone platform, a tablet platform or a set-top box platform, for example.”
One of the main advantages of the new platform is cost reduction by efficient layer reduction, optimized interconnect paths, and streamlined/automated control of the design process. “What’s really changing with IoT and with TSVs and expensive packages is people now want to do cross-domain exploration or path finding,” Park said. People evaluate options largely based on cost, performance and reliability. For example, designers want to look at the pros and cons if they take DRAM off the board and move them into the package.