The June 22-23 FDSOICE workshop, which will be on the MINATEC campus, brings together experts from academia, semiconductor companies, system-design houses and the EDA industry to present a vision of the strategic directions and state-of-the-art in FD-SOI IC design. Specific topics cover the FD-SOI food chain: applications, process roadmaps and manufacturing technologies, energy-efficient architectures and power management, circuit-design techniques, body-bias techniques, modeling, characterization and design enablement.
In addition to keynotes by Thomas Skotniki from STMicroelectronics and Prof. Boris Murmann from Stanford University, the workshop’s 30 presentations will cover the whole knowledge chain and the market value chain from academia and industry. Highlights of the presentations include:
- ST, GLOBALFOUNDRIES and Samsung will cover FD-SOI manufacturing offers
- Ciena, ST and NXP will discuss products based on FD-SOI chips
- Cadence, Synopsys, Mentor Graphics, sureCore, eSilicon and Tiempo will explain their offers for FD-SOI in terms of IP and EDA tools
- Prominent professors from world-class universities (ETH Zurich, University of Bologna, University of Kyoto, University of California, Berkeley) will present their innovations to design with FD-SOI
- Leti will present state-of-the-art research in FD-SOI and facilities available to partners willing to start design with FD-SOI
Visit LetiDays Grenoble registration details and other information about the conference on June 24-25, and associated workshops and seminars on June 22, 23 and 26.