Process Watch: Risky Business

By Douglas G. Sutherland and David W. Price

Authors’ Note: This is the ninth in a series of 10 installments that explore certain fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights its implications. Within this paper we will use the term inspection to imply either defect inspection or a parametric measurement such as film thickness or critical dimension (CD).

Previous installments have discussed many aspects of process control from general concepts to specific issues related to risk management (see below for links to previous Process Watch articles). In this article we will focus on strategies for managing risk associated with the most difficult steps in the process.

The ninth fundamental truth of process control for the semiconductor IC industry is:

High-Stakes Problems Require a Layered Process Control Strategy

In the IC manufacturing process there are a bewildering number of things that can go wrong and there is a tremendous amount of money at risk. As the margins of error steadily decrease with each new design node, the number of parameters that can wreak havoc on the process continues to rise. The increasing complexity of multiple patterning, pitch splitting and other advanced patterning techniques does nothing to mitigate this problem.

This increased process complexity drives the need for new process control strategies. For example, higher order overlay corrections that were largely unheard of above 45nm are now considered mandatory at 2Xnm and below. Similarly, wafer topography, something that historically was only measured during the manufacture of bare wafers, is now becoming a requirement in IC fabs to accommodate the shallower depth of focus in today’s scanners. For the same reasons, wafer backside and edge inspection are also becoming common practices. The difficulty of some process steps necessitates that they have more than just a single line of defense.

Figure 1 below shows the severity of a potential problem increasing in the horizontal direction and the probability of that problem actually occurring increasing in the vertical direction. In this figure the term “risk” can be thought of as the product of these two attributes – the amount of material impacted (severity) multiplied by the probability of it happening. The severity could increase for a number of reasons: the next inspection point could be many steps downstream from the current step, the process tools at the current step may have very high throughput so that by the time the problem is identified many lots have been exposed to it, or both.

Figure 1. Risk exposure chart with higher severity to the right and higher probability to the top. The problems that require a layered approach to risk management are those in the upper right hand corner where the probability of having a problem is high and the amount of material exposed to that problem is large.

Figure 1. Risk exposure chart with higher severity to the right and higher probability to the top. The problems that require a layered approach to risk management are those in the upper right hand corner where the probability of having a problem is high and the amount of material exposed to that problem is large.

Clearly the safest place to operate is in the lower left corner where both probability and severity are low. However, for process steps that are inherently closer to the upper right hand corner of the chart—high probability and high severity—it often makes sense to have a layered approach to process control in which there is a well thought out back-up plan if the problem is not immediately identified with the first inspection step. Sometimes there are aspects of the problem that are easier to detect later in the process than immediately after the problem step.

Consider the case of forming the first metal layer that wires together the individual transistors. This can be particularly difficult for a number of reasons. The CDs and pitches are aggressive—often at design rules similar to the gate layer. Also, the opportunity for built-in redundancy (multiple vias) is low because there is only one point of contact for each of the transistor connections (source, drain and gate), so every connection has to work.

In such a case it makes sense to have multiple layers of protection, each of which has unique capabilities. For instance, you might perform macro inspection after the photo step to discover any gross defects in the lithography process. There should also be inspection steps after oxide etch, barrier deposition and copper CMP. Having multiple inspection steps ensures the quality of the process throughout the formation of this layer and also helps ensure that you catch problems that originate at one step but may not become apparent until later in the process.

Simply waiting to do a final inspection at copper CMP is usually not sufficient. Doing so will pick up problems in the CMP process but may not allow for distinguishing these from issues that may have originated at an earlier step. Only by inspecting the same wafer at multiple steps are you able to subtract out previous-layer defects and isolate the problem.

Having multiple inspection points has several benefits. It helps identify problems early in the process flow, which significantly reduces the amount of material exposed. A device with 50,000 wafer starts per month has about 1,600 wafer starts per day. Identifying a problem one day sooner can save millions of dollars (depending on the yield loss and wafer cost). Multiple inspection points also help diagnose where the problem occurred and expedite the recovery procedure. Over time, they provide more information about the process allowing for continuous improvement plans that can help reduce not only the severity but also the frequency of problems.

Previous Process Watches:

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Drs. Price and Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

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