Applied Materials, Inc. today announced that Dr. Chorng-Ping Chang, who leads the company’s strategic external research with universities and industry consortia, has been named a 2016 IEEE Fellow. Dr. Chang is being recognized for his contributions to “replacement gate and shallow trench isolation for CMOS technology,” which have had a profound impact on the advancement of integrated circuit (IC) fabrication. The IEEE Grade of Fellow is conferred by the IEEE Board of Directors upon a person with an outstanding record of accomplishments in any of the IEEE fields of interest. IEEE Fellow is the highest grade of membership and is recognized by the technical community as a prestigious honor and an important career achievement. The total number selected in any one year cannot exceed one-tenth of one-percent of the total voting membership.
“Chorng-Ping’s brilliant work helped the industry adopt novel methods in CMOS scaling and made important contributions to the performance, functionality and size of the electronic products we use every day,” said Dr. Om Nalamasu, senior vice president and CTO of Applied Materials. “I commend him on this well-deserved honor and for his efforts leading Applied Materials’ collaborations with universities and consortia.”
Dr. Chang’s outstanding technical contributions and extensive semiconductor industry community service span nearly three decades. While working at Bell Laboratories he led pioneering research that helped the industry through one of the most significant transitions in the history of CMOS technology - the shift from the gate-first to the gate-last (replacement gate) process. His work on extending the use of replacement gate technology continued at Applied Materials, and today virtually all state-of-the-art CMOS logic devices, including FinFET transistors, use replacement gate technology. In addition, early on in his career Dr. Chang made pivotal contributions in deposition, etching and advanced plasma processing technologies.
Another critical area where Dr. Chang made significant contributions is advanced shallow trench isolation (STI). He led an early detailed study that demonstrated how changing the shape of the top trench corners helped resolve serious issues of defect density, junction leakage and device threshold voltage control. This research had a long-term impact on the robustness and extendibility of STI in mainstream CMOS manufacturing, to the extent that major CMOS process technologies introduced in recent years have used STI corner engineering techniques developed by Dr. Chang and his team.
Dr. Chang has served the IEEE community in several facets throughout his career, including as editor of IEEE Electron Device Letters for 12 years. He has also been a member of the program committees of various international technical conferences on IC technology, and is currently the U.S. Chair of the International Technology Roadmap for Semiconductors (ITRS) Process, Integration, Devices and Structures Chapter. Dr. Chang holds a bachelor’s degree from National Tsing Hua University and a Ph.D. in engineering from the University of California, Berkeley.