Practical limits for metallization scaling in fabs

Beyond economic limits due to litho limitations, the inherent need for a physical barrier puts an electrical limit on the ability to scale.

BY ED KORCZYNSKI, Senior Technical Editor

On-chip interconnects for ICs have evolved to meet different exacting needs, and the most advanced chips require multiple levels of copper (Cu) metal lines and via connections between transistors. When scaling Cu lines to the finest dimensions possible to interconnect local transistors in advanced manufacturing nodes, there are economic limits due to lithography technology. Also, the inherent need for a physical barrier to surround Cu and prevent poisonous out-diffusion imposes an electrical limit on the ability to scale. Best practices today include an explicit hierarchy of dimensions and a stacking-order for on-chip interconnects: local between nearby transistors, global between functional blocks, as well as input/output (I/O) and power/ ground connections. With advanced logic chips having >12 levels of on-chip copper metallization, only the bottom-most are at the tightest pitch. Table1 (courtesy of imec) shows the hierarchy of interconnect signals for a 14nm-node finFET logic chip, and the tightest pitch is 42nm as used for the vertical gate contacts as well as for the metal-1 (M1) and metal-2 (M2) levels. The last published International Technology Roadmap for Semiconductors (ITRS) chapter for Interconnects that included detailed tables of on-chip metal specifications was published in 2012. In the ITRS 2012 Interconnect chapter Table 2 on microprocessor (MPU) requirements, the “Intermediate Wires” specification for Metal 2 (M2) is the same as for Metal 1 (M1) level and shows 32nm half-pitch is manufacturable, which is used with MPU physical gate lengths of 22nm.

interconnects table

FIGURE 1 shows the fraction of the intermediate wire volume that is Cu depending on the thickness of the barrier for succeeding generations of high-performance (HP) MPUs. Note that in the SEM cross-section on the right that the 10nm of Cu is only 50% of the line thickness, and that such a line would be extremely susceptible to current-crowding and premature circuit failure due to electro-migration (EM).

interconnects 1

In minimally-scaled Cu wiring, resistivity increases arise due to electron scattering from the sidewalls and grain boundaries. Tricky process integration involving electro-chemical deposition (ECD) of the Cu along with careful thermal annealing is already being used to grow large columnar grains across the trench—resembling bamboo when cut in cross-section—to minimize the volume of grain-boundaries. Forming columnar lines of single Cu grains after ECD requires control of barrier atomic-layer deposition (ALD) parameters, along with chemical-mechanical planarization (CMP) and rapid-thermal annealing (RTA) processes.

When engineering materials, first-order parameters to be controlled include composition and uniformity, while second-order parameters include internal structure such as crystal orientation or average crystal grain-size in multi-crystalline structures. In general, it is more difficult and far more expensive to control second-order parameters in manufacturing, and when engineering at the atomic scale it is yet more difficult to control third- order parameters such as grain boundary orientation.

Since the industry must control third-order parameters to continue using Cu metal, there has been ongoing R&D of non-metallic materials that could be integrated into ICs as on-chip conductors. Superconductors have been found that can exhibit zero resistance to electric current flow, but only when they are frozen to extremely low temper- atures such that phonon vibrations within their lattices settle out. Recently, a team of six Japanese research groups tested nearly 1000 materials over a four year period and found no superconductors with critical temperatures (Tc) above the 298°K of room temperature.

The rapid increase in resistivity when Cu lines are scaled to minimal dimensions motivates the search for “ballistic” conductors which are immune from electron scattering effects. While R&D into graphene and Carbon Nano-Tubes (CNT) as on-chip conductors continues, there are inherent issues with integrating any such technologies into high-volume manufacturing (HVM) to achieve superior performance compared to legacy Cu. The ITRS 2012 Interconnects chapter summarizes the issues:

Ballistic transport in one dimensional systems, such as silicides, carbon nano tubes, nanowires, graphene nanoribbons or topological insulators offers potential solutions. While ballistic transport has many advantages in narrow dimensions, most of these options incur fundamental, quantized resistances associated with any conversions of transport media, such as from Cu to CNTs. In addition to the quantum resistance, the technological problems of utilizing an additional conduction medium with its interface, substrate and integration issues, pose substantial barriers to the imple- mentation of ballistic transport media.

Imec recently published preliminary “7nm-node” finFET specifications for logic ICs having 14nm gate lengths, with expectation that delays in the implementation of EUV lithography call for use of multiple-patterning using 193-immersion (193i). M1 layer patterning at 18nm half-pitch can be done with self-aligned double- patterning (SADP) technology, while Litho-Etch-Litho- Etch (LELE) patterning with two masks allows for 24nm half-pitch patterning of more arbitrary 2D shapes for easier routing. Going to tighter half-pitches will require Litho-Etch-Litho-Etch-Litho-Etch (LELELE) with three masks, or self-aligned quadruple patterning (SAQP) schemes, which is why the number of metal levels for logic continues to increase with each successive node.

In memory chips with regular bit arrays for storage and orthogonal bit:word architectures, leading 3D architectures use similar metal interconnect half-pitches. FIGURE 2 shows a new 3D stacked NAND Flashmemoryarchitecturethatwill be shown at the 2015 IEEE International Electron Device Meeting (IEDM) in presentation 3.2, “A Novel Double-Density, Single-Gate Vertical Channel (SGVC) 3D NAND Flash That Is Tolerant to Deep Vertical Etching CD Variation and Possesses Robust Read-disturb Immunity,” by Hang-Ting Lue et al. of Macronix.

interconnects 2

The Metal Level 2 Bit Line (ML2 BL) half-pitch of ~25nm in parallel lines in this 3D NAND structure can be formed with SADP litho. Since SADP has been used in HVM of 2D NAND cells, presumably the complex SADP integrated process flow has already been established. Imec has shown ability to reach 18nm half-pitch with SADP 193i, so this new 3D NAND structure might be able to be shrunk by a “half-node” without having to re-engineer the ML2 BL fab process flow.

Even if the lithographic cost of scaling metal lines to <18nm half-pitch could be managed, the Cu barrier provides a functional limit as shown in Fig. 1. Assuming that Cu multi-level interconnects will be current-limited and will require ~3nm barriers—to prevent out-diffusion from the line as well as EM-induced diffusion within the line—the industry is already considering atomic limits. The barrier would be ~1/3 of 18nm, ~1/2 of 12nm, and ~2/3 of 9nm wide Cu lines.

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