NanoFocus AG introduces new inspection system for semiconductors industry

NanoFocus AG, the developer and manufacturer of optical 3D surface measuring technology, introduces the new measuring system µsprint hp-opc 3000 for the optical inspection of probe cards within the framework of the 26th Annual SW Test Workshop in San Diego from 5th - 8th June 2016.

nanofocusµsprint hp-opc 3000 enables an innovative and future-oriented process step in wafer production. The process is specially designed for the requirements of wafer test locations with a variety of different probe cards as well as large-volume throughput. A pilot system is already installed at a renowned manufacturer of semiconductor elements.

Probe cards are special test devices that are used for standard function tests of wafers at the end of the so-called front-end process. This means, they are used after the functional structures of the electronic elements on a wafer are fully manufactured. The µsprint hp-opc 3000 system is responsible for ensuring that the wafers are in sound condition after testing, for reducing yield losses as well as for minimizing the time and number of complex maintenance cycles the probe cards are subjected to regularly.

As wafers already completed the most important part of value creation with the manufacturing of the functional structures, damage during testing represents a significant economic loss. Furthermore, faulty probe cards can cause damage during wafer testing. Although such faulty probe cards can lead to a correct result of the functional test, they can cause unnoticed damage to a wafer rendering it unusable. On the one hand, such incidents represent an economic loss due to recall actions, on the other hand, a minimized quality perception of the delivered products by the customer. Beyond that, using the µsprint hp-opc 3000 can shorten and/or specify repair cycles more clearly. This provides an important contribution to the reduction in operative costs when using probe cards.

µsprint hp-opc 3000 is a process-capable capacity tool. It can be integrated into process control systems via a SECS/GEM communication interface. The tool complies with all necessary and common standards required at front-end wafer test locations.

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