Coventor wins “Best of West” Award

By Pete Singer, Editor-in-Chief

On Wednesday, Solid State Technology and SEMI announced the recipient of the 2016 “Best of West” Award — Coventor — for its SEMulator3D. The award recognizes important product and technology developments in the electronics manufacturing supply chain. The Best of West finalists were selected based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact.

Coventor won the “Best-of-West” award for its SEMulator 3D modeling software. Left to right, SEMI’s Karen Savala, Dinesh Bettadapur, vice president, business development at Coventor, who received the award, and Pete Singer, Editor-in-Chief of Solid State Technology.

Coventor’s SEMulator3D is a 3D semiconductor process modeling platform that can predictively model any fabrication process applied to any semiconductor design. Starting from a “virtual” silicon wafer, the product performs a series of unit processes like those in the fab to create highly accurate 3D computer models of the predicted structures on wafer.

“It’s a very powerful software modeling platform that has been widely adopted for advanced process development and integration for 10nm, 7nm nodes and beyond,” said Dinesh Bettadapur, vice president, business development at Coventor. Bettadapur accepted the award in the Coventor booth, presented by Solid State Technology’s Pete Singer and SEMI’s Karen Savala.

Bettadapur noted that advanced devices are increasingly becoming 3D, whether it’s finFET structures, 3D NAND or gate-all-around. “We enable you to both visualize the device you’re trying to build in advance without running a single wafer, and also accurately predict process variations,” he said.

Using unique physics-driven 3D modeling technology, the SEMulator3D modeling engine can model a wide variety of unit process steps. Each process step requires only a few geometric and physical input parameters that are easy to understand and calibrate. Just as in an actual fab, upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity, etc.) interact with each other and design data in a complex way to impact the final device structure.

“You can analyze any process variation, whether it’s film thicknesses, sidewall angles, etch depths, litho biases and so forth. You can vary any process parameter that you have entered in our process simulator and then look at the upstream and downstream process effects,” Bettadapur said.

Starting from input design data, SEMulator3D follows an integrated process flow description to create the virtual equivalent of the complex 3D structures created in the fab. Because the full integrated process sequence is modeled, SEMulator3D has the ability to predict downstream ramifications of process changes that would otherwise require build-and-test cycles in the fab.

On display at Coventor’s booth is 3D sculpture modeled on 14nm FinFET Technology (see photo). This piece received the grand prize at the Design Automation Conference (DAC) last month.

The piece was produced on a state-of-the-art 3D printer from Stratasys, using SEMulator3D to generate the data. The effort was supported by GrabCad, a digital manufacturing hub that helps designers and engineers build great products faster.

With SEMulator3D, Coventor created a large model of 14nm FinFET transistors, across a wide area of SRAM design, at high resolution, integrated from starting wafer through Metal 3, with some artistic cut-outs for visibility.   The resulting model reinforced all the key advanced capabilities of SEMulator3D, including multietch, visibility-limited deposition, selective epitaxy and many others.

As DAC grand prize winner, the 14nm FinFET 3D Sculpture will now be moved to the Computer History Museum in Mountain View, CA where it will be on display for one year.

Hear more about the SEMulator 3D and all of the Best of West finalists today at the Best of West Showcase in the Advanced Manufacturing Forum at TechXPOT South from 2:00pm-3:30pm.

SEMulator3D Viewer, showing a hypothetical 22nm FinFET SRAM cell

SEMulator3D Viewer, showing a hypothetical 22nm FinFET SRAM cell


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