With its unique characteristics, FD-SOI is generating increasingly strong interest from major players in the semiconductor ecosystem for a very wide range of markets.
BY MANUEL SELLIER, Soitec, Bernin (Grenoble), France
Fully depleted silicon-on-insulator or FD-SOI is the only technology bringing together two substantial characteristics of CMOS transistors: 2D planar transistor structure and fully depleted operation. It relies on a unique substrate whose layer thicknesses are controlled at the atomic scale. FD-SOI offers remarkable transistor performance with one of the best power, performance, area and cost tradeoffs (PPAC) among all advanced CMOS technologies. In addition, FD-SOI has numerous other unique advantages including back bias ability, very good transistor matching, near threshold supply capability, ultra-low sensitivity to radiation and very high intrinsic transistor speed, which allows it to handle mmWave frequencies.
All these key features are progressively making FD-SOI a de facto technology for many applications including entry-level application processors for smartphones, system-on- chip (SoC) devices for autonomous driving and IoT, and all mmWave applications such as 5G transceivers and radar systems for automotive electronics.
FD-SOI technology is supported by multiple foundries and IDMs with full technology offerings now available for the 28nm and 22nm nodes and emerging for the 65nm and 12nm nodes. With this global ecosystem in place, FD-SOI is ready for applications development for diversified markets.
There are several striking characteristics of FD-SOI substrates that give this technology unique advantages. This article summarizes the latest advances and the various elements of the global ecosystem that supportwidespread implementation of FD-SOI as well as the applications that most benefit from it.
The heart of FD-SOI
Everything in FD-SOI technology starts with the substrate. The substrate directly defines the transistor architecture, as shown in FIGURE 1. To allow the fully depleted operation of transistors, the thickness of the top silicon layer defining the device channel represents a real challenge, with the thickness target typically around 60 Å or 11 atomic layers. Given the consumption of silicon material during device fabrication, a 120 Å incoming top silicon specification is usually required by foundries. Uniformity is another very challenging specification needed to keep transistor variability as low as possible. Uniformity of +/-5 Å or 1 atomic layer is typically considered essential. Buried oxide (BOx) thickness also must be very thin - around 20nm - to maximize electrostatic control in the transistor channel due to the ground plane effect.
Manufacturing a 300mm piece of crystalline silicon with a thickness specification as low as 11 +/-1 atomic layers is understandably difficult. Ten years ago, it sounded unachievable so people studied other paths to enable fully depleted transistors . But it is now possible.
Fabrication relies on the well-known Smart Cut TM process (FIGURE 2). As shown, wafer A first undergoes an oxidation step followed by high-dose ion implantation, creating a weakened layer just beneath the surface. After careful cleaning steps, wafer A is bonded to wafer B through molecular-bonding technology. Splitting is then induced at the precise location of the weakened zone of wafer A. Finally, the formed SOI wafer is subjected to other smoothing process steps to achieve the targeted thickness specification. It is noteworthy that high-quality wafer A can be recycled for further reuse, making Smart Cut the most cost- effective solution for SOI manufacturing.
The FD-SOI substrate-manufacturing process is now fully mature. In particular, thickness uniformity is very well controlled at all levels, from transistor to wafer, as shown in FIGURE 3. This ensures a very low level of transistor variability.
When less is more
The way of getting more performance out of silicon below 28nm node adds more complexity to the manufacturing process. Consequently, as illustrated in FIGURE 4, the smaller nodes get, the greater number of masks are needed to create chips. This increases manufacturing costs as well as other non-recurring engineering costs including design flow, design verification, mask sets and more.
On the other hand, FD-SOI is a simple technology from a manufacturing standpoint. In fact, it offers more perfor- mance while decreasing the manufacturing process complexity. Most of the channel engineering work is actually done directly at the substrate level, making FD-SOI easier to implement than bulk silicon, as major foundries have reported  .
The next level of transistor performance
In addition to simpler manufacturing, FD-SOI offers other substantial benefits, as depicted below and summarized in FIGURE 5.
1. Better design flexibility through body bias
The thin BOx of FD-SOI not only enhances electro- static control of the channel, but also makes it possible to completely tune the threshold voltage through back biasing. All the complex Vth adjustment techniques through channel doping can be avoided. Low, mid-range and high Vth can be achieved simply through back-gate polarization. The thin BOx behaves like a real second gate and, most importantly, it can be used dynami- cally. This means that the same functional block can operate under high or low power, on demand. Back bias potential is huge: selective body bias for critical path improvements , process variation compensation  and reliability drift compensation . Full back biasing is a very unique feature, only achievable with SOI on thin BOx technology.
2. Power-performance-area-cost tradeoff: Best PPAC of all planar technologies.
Thanks to simpler manufacturing, better control of random mismatch, minimizing of junction leakage and capacitances, enhanced electrostatic control through fully depleted transistor operation and the possibility of tuning body bias, FD-SOI technology presents the best power- performance-area-cost tradeoff (PPAC) among all planar technologies.
3. Ultra-low power through near-threshold supply voltage
Almost all CMOS technologies achieve their best energy efficiency – i.e., the lowest amount of energy per function, regardless of the frequency – at around 0.4 V supply voltage, often referred to as Vdd . At this level of supply voltage, variability management is a real challenge. Thanks to body bias and to its intrinsic low-variability characteristics, FD-SOI can achieve very low supply voltages. More generally, the ability to lower the supply voltage, although not necessarily as low as 0.4 V, is a real challenge in many applications in which power is a greater challenge than performance. Given the fact that dynamic power scales with Vdd2, a technology like FD-SOI that is capable of strong power savings through tremendous supply voltage reduction presents a unique advantage.
4. Best RF-CMOS technology with almost 2 times maximum frequency over 3D devices
Integrating as many analog/RF functions as possible into a single RF-CMOS silicon platform is becoming an increasingly important issue in many markets for obvious cost and power reasons. However, one limitation of RF-CMOS platforms is the limited ability to increase frequency, especially in the mmWave spectrum (30 GHz and above). This is a bigger issue with 3D devices such as FinFETs, which must carry very strong parasitic capaci- tances due to their 3D structures . As a result, SiGe- Bipolar platforms are often used for this frequency range. FD-SOI is a planar technology and, as such, it should not suffer from the limitations of 3D devices. Ft/Fmax in the range of 325-350 GHz have been reported , allowing full usage of the mmWave spectrum up to 100 GHz and giving FD-SOI RF-CMOS platforms a bright future in many applications.
5. Enhanced reliability
Low sensitivity to high-energy particles is another key characteristic of FD-SOI. High-energy particles can interact with silicon and generate a significant amount of charges capable of flipping transistor logic state, thus increasing the soft errors rate (SER). FD-SOI devices are completely isolated from the substrate due to the BOx layer. This means that any charge generated in the substrate is unlikely to modify the device logic state. In short, FD-SOI is much less sensitive to SER . This has very important consequences for safety-critical devices such as autonomous car systems.
6. Outstanding analog transistor characteristics
Often, analog designers have to make their designs work with more and more degraded transistors as technology shrinks. Meeting speed, noise, power, leakage and variability requirements is increas- ingly challenging. By providing a transistor with improved matching, gain and parasitic, FD-SOI can greatly simplify device design . Moreover, the back bias has potential for the design of many new analog structures .
FD-SOI’s growing use at foundries
Some of the most pioneering work with FD-SOI has been done at semiconductor foundries around the world.
STMicroelectronics adopted FD-SOI technology in 2012  and started several projects. The company demonstrated an ARM-based application processor for smart-phones with 3 GHz+ operating frequency on 28nm FD-SOI . The technology is now used at STMicroelectronics for many diversified markets  .
In 2014, Samsung announced the adoption of 28nm FD-SOI technology for its foundry division . Mass production maturity was reached in 2016 , and the first product release was announced recently  .
In 2015, GLOBALFOUNDRIES developed a 22nm FD-SOI technology called 22FDX , which it positioned as offering the best performance/cost ratio. This FD-SOI technology platform achieved performance close to 16nm/14nm FinFET at a cost similar to 28nm bulk silicon . The first commercial product was announced in February 2017 by GLOBALFOUNDRIES and Dream Chip Technologies . GLOBALFOUNDRIES’ technology is now almost fully qualified, with volume ramp-up expected this year.
In Asia, the Chinese foundry Huali has announced its intention to include 22nm FD-SOI technology in its fab2 plan , offering the Chinese market greater access to FD-SOI technology.
In Japan, Renesas’ experience with FD-SOI includes work on a very low-power FD-SOI technology called silicon- on-thin-BOx (SOTB), which targets low-power MCU markets. This technology has been supported by the LEAP initiative (Low-Power Electronics Association and Project) and is now available in 65nm. Renesas has reported very low-power consumption with this platform, as small as a tenth of that achieved using bulk silicon.
IP/CAD status and roadmap
The design ecosystem is well established for 28nm FD-SOI with complete libraries and foundation IP and growing at a fast pace for 22nm technology. EDA companies are on board and developing IP ported to FD-SOI.
In September 2016, GLOBALFOUNDRIES announced a new partner program called FDXceleratorTM to facil- itate 22FDX SoC design and reduce time to market for its customers including Synopsys, Cadence, INVECAS, VeriSilicon, CEA-Leti, Dream Chip and Encore Semi . In December 2016, the foundry announced the addition of eight new partners to its growing FDXcel- erator program including Advanced Semiconductor Engineering (ASE Group), Amkor Technology, Infosys, Mentor Graphics, Rambus, Sasken, Sonics and Quick- Logic .
As for the technology roadmap, FD-SOI is available on a wide range of technology nodes from 65nm to 12nm with visibility down to 7nm. Building on the success of its 22FDX offering, in 2016 GLOBALFOUNDRIES unveiled a new 12nm FD-SOI semiconductor technology called 12FDX . Staying with fully depleted planar processing allows the foundry to take advantage of the low parasitic capacitance, avoid the complex lithog- raphy steps required by equivalent 3D transistors, and leverage back biasing to boost transistor performance, especially at low supply voltages. Customer product tape-outs are expected to begin by the end of 2017.
Leti, which pioneered FD-SOI development 15 years ago, worked with GLOBALFOUNDRIES on the 22FDX and 12FDX platforms. The organization recently developed test devices on 10nm FD-SOI technology and produced models for 10nm and 7nm on FD-SOI. Leti strongly believes that FD-SOI can be scaled down to 7nm.
Both Samsung and GLOBALFOUNDRIES plan to have embedded non-volatile memory integrated into their FD-SOI technology platforms by 2018  .
FD-SOI traction in power and analog/RF integration ThankstothegrowingmaturityoftheFD-SOIecosystem, there is now a wide range of applications seeing strong differentiation possibilities through FD-SOI. These include single-chip solutions for entry-level mobile communications, general purpose application processors, image signal processors, SoC for set-top boxes, embedded computer vision, microcontrollers, mixed-signal applications such as transceivers, GPS/satellite receivers, wi-fi/ BT combos and mmWave radar systems.
For all these applications, power budget is typically very limited and must be balanced with performance targets. A good example of this can be found in embedded computing applications such as ADAS, where designers must constantly find compromises to achieve the required performance with a very limited power budget, typically around 3 W. For all embedded computing applications, FD-SOI - and its ability to run on very low supply voltages - is gaining momentum as the reference technology.
In addition, RF/analog integration is often key for these applications. Having best-in-class RF-CMOS technology available on the same silicon die as the digital parts is a unique advantage of FD-SOI. It opens up possibilities for single-chip solutions covering a wide range of functions. This is particularly advantageous in entry-level markets such as low-end mobile, where the price pressure is so great that integration must be pushed to its limits, or in mmWave applications including radar and 5G transceivers, where the mmWave RF functions can be integrated on the same die as the computing functions.
A new wave of ground-breaking products
The list of FD-SOI-based products is increasing at a very fast pace, with multiple product announcements over the past months.
In September 2016, Huami (a Xiaomi partner company) introduced a new fitness smartwatch that includes a FD-SOI-based global positioning system (GPS) chip demonstrating record energy efficiency (FIGURE 6) . The chip allows the watch to reach an unsurpassed battery life of 35 hours with the GPS turned on, which represents two to five times more than today’s similar devices. The chip, revealed in February 2016 at the International Solid- State Circuits Conference (ISSCC) in San Francisco , dramatically lowers power usage and opens the door for always-on GPS applications in smartwatches, smart-phones, drones and a large number of devices for the IoT.
Also in 2016, Mobileye posted on its website that its next EyeQ4 product family dedicated to level3 autonomous driving will be based on FD-SOI technology  (FIGURE 7).
In March 2017, NXP released two general-purpose processor families (i.MX7ULP and i.M8X)   based on Samsung’s 28FDS FD-SOI technology for ultra-low power consumption and rich graphics in battery-powered applications (see NXP roadmap FIGURE 8). NXP reported a deep-sleep suspended power consumption of 15 μW or less for its i.MX7ULP product, 17 times less in comparison to previous low-power bulk devices, while the dynamic power efficiency improved by 50 percent. This high-performance, low-power solution is optimized for customers developing IoT, home control, wearable and other applications that spend a significant amount of time in standby mode with short bursts of performance-intense activity that require exceptional graphics processing.
In March 2017, Eutelsat Communications and STMicroelectronics announced a new-generation SoC for interactive applications that represents a step down in the overall cost of interactive satellite terminals while reducing power consumption .
On the 22nm side, Dream Chip announced the industry’s first 22nm FD-SOI product for a new ADAS SoC for automotive computer-vision applications . The SoC device (FIGURE 9) offers high- performance image acquisition and processing capabilities and supports convolutional neural network (CNN) vision workloads to meet the demand for complex automotive object detection and processing.
The 22nm FD-SOI product portfolio is expected to grow significantly in the coming year as the technology ramps up.
Adding fabs to meet overall FD-SOI demand
Faced with the growing interest of FD-SOI, particularly in China, foundries are organizing themselves to build up enough production capacity. In February 2017, GLOBALFOUNDRIES announced plans to expand the capacity of its Fab 1 facility in Dresden by 40 percent by 2020. Dresden will continue to be the center for FDX technology development .
In China, GLOBALFOUNDRIES and the Chengdu munici- pality have announced a partnership to build a fab. The partners plan to establish a 300mm fab to support the growth of the Chinese semiconductor market and to meet accelerating global customer demand for 22FDX . The fab will begin producing mainstream process technologies in 2018 and then focus on manufacturing GLOBALFOUNDRIES’ commercially available 22FDX process technology, with volume production expected to start in 2019.
With these two announcements, GLOBALFOUNDRIES will have a future production capacity of more than 2 million FD-SOI wafers per year.
Regarding FD-SOI substrate manufacturing capacity, Soitec owns one 300mm fab in France and has another one in Singapore (currently in standby mode) with a combined global capacity of 1.5 million wafers per year (for manufacturing FD-SOI and other emerging SOI products). The company has plans to go beyond that to meet additional customer demand.
Growing interest in FD-SOI reflects today’s new paradigm for semiconductor technologies. Customers are demanding for more computing capability with drastically reduced power consumption, enabled by enhanced analog/RF integration. With its unique characteristics, FD-SOI is generating increasingly strong interest from major players in the semiconductor ecosystem for a very wide range of markets, especially for embedded computing applications. FD-SOI is now a mainstream technology, which device designers are leveraging for key competitive advantages.
The author would like to warmly thank the Soitec team (Christophe Maleville, Bich-Yen Nguyen, Thomas Piliszczuk, Alexandra Givert, and Camille Dufour) for their valuable contribution and constructive discussions.
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