This work explores the effect of underlying metallic alloys and the influence of Cu loss under via bottom after dry etching and wet cleaning processes. To Improve the Cu loss under via bottom, effective approaches are proposed. The modified actions for via bottom improve not only wafer yield but also reliability of the device.
By CHENG-HAN LEE and REN-KAE SHIUE, Department of Materials Science and Engineering, National Taiwan University, Taiwan, ROC
With metal line dimensional shrinkage in advanced packaging, Cu voids in metal lines cause the failure of via-induced metal-island corrosion. It impacts not only yield loss but also device reliability, specifically electron migration (EM) and stress migration (SM). One of the Cu voids is located under via bottom which is more unpredictable than others. The Cu void under via bottom is caused by integrated processes such as via etch and Cu electro-chemical plating (ECP). It is not similar to the Cu void caused by barrier Cu-seed and ECP Cu. The mechanism of Cu voids under via bottom formation from dry etching and wet cleaning are related to Cu dual-damascene interconnection. Both plasma damage and chemical reaction are proposed to explain its failure mechanism. In the integrated process of Cu interconnects, we can design not only the safety dimension of Cu line via depth but also process criteria with less damage and oxidation in dry etching and wet clean based on Cu loss amount (Cu recess) in TEM inspection. The modified actions for via bottom improve not only wafer yield but also reliability of device.
For deep sub-micrometer CMOS integrated circuit, copper (Cu) metallization has been applied in semi- conductor metallization processes of ULSI beyond 0.13 μm technology because of its lower resistivity and better reliability, especially better electron migration resistance than that of aluminum (Al) [1–4]. Under 10 nm technology, front end-of-line (FEOL) device process had already transferred from planar to fin-fet MOS, but the Cu formation process only have slight change in backend-of-line (BEOL) metallization. There are two kinds of schemes, single- and dual- damascene processes. In fact, the main body of Cu interconnection in dual- damascene process includes metal trench and via etching, post etching, wet clean, deposition of barrier films and Cu-seed layer, Cu ECP and Cu chemical mechanical polishing (CMP). They are all similar technologies.
Even though many well-known modifications were implemented in both mature and advanced processes, a few lethal defects which significantly damage wafer yield and device reliability, such as Cu voids and scratches, always exist after Cu-CMP process due to the Cu metal corrosion. Most previous studies in Cu voids, such as Lu et al. , Song et al. , Wrschka et al.  and T.C. Wang et al. , were focused on Cu voids on metal line due to wafer yield concern. It meant that Cu voids on metal line could be detected by on-line electron-beam inspection as demonstrated by Guldi et al. .
Although Reid et al.  have described that the formation of Cu voids could be resulted from step coverage of Cu-seed, waveform function and additives (Accelerator, Suppressor and Leveler), chemical formulation of ECP. However, the mechanism of Cu voids during the via-formation process is still unclear. Coverage or quality of seed layers being poor, thin and/or discontinuous will induce via bottom void which results in deteriorating the plating process. A systematic study of Cu void effects has not been reported. For the mature technology to reduce via resistance, a Cu surface cleaning (pre-cleaning) process prior to deposit the diffusion barrier metal to remove the CuOx on via bottom in order to improve yield was mentioned by Wang et al. . However, it caused a significant Cu loss under via bottom as well as deteriorating reliability window of the process.
With the metal line shrinkage in advanced CMOS process, Cu void under via bottom becomes much crucial than before. Actually, it perhaps is the most important defect in device reliability concern. Unlike Cu voids or pits on metal line, such defects cannot be easily detected by on-line defect screen methodology, neither electrical test nor wafer yield testing. The reason is that Cu interconnection is still valid at that time. The most decisive step of Cu void detection under via bottom is the reliability test. Alers et al.  showed that Cu voids affected electron migration resistance. Wang et al.  had pointed out that Cu voids under via bottom were the major factor resulting in failure during stress and/or electron migration tests. In our exper- iment, Cu loss under via bottom was strongly related to high temperature storage (HTS) and high temperature operation life (HTOL) reliability tests. Thermal and/or electronic stresses may resulted from many processes, including Si manufacturing, bumping, wafer yield test and even early failure rate (EFR) stage in reliability test. It should be further clarified.
A. Cu scheme and process
A via structure consisted of metal chains and via holes as displayed in FIGURE 1. Dual Cu damascene with “via first” process was applied to prepare the test sample. The Cu interconnection was made by BEOL Cu dual-damascene process which included an etching stop layer, dielectric deposition, metal line/via lithography, metal line/via dry etching, post etching wet clean containing deionized water (DIW) with discharging gas, deposition of barrier films and Cu-seed layer, Cu ECP and Cu CMP.
In advanced technology, EM resistance decreasing with metal line shrinkage of Cu interconnects was a major concern, specifically for dimensions of metal line and via bottom less than 30 nm. As the interconnect dimension shrunk, the EM resistance of Cu interconnects was deteriorated and decreasing the service life of device. In order to improve EM resistance of Cu damascene, doping the Cu interconnects with appropriate elements was one of engineering approaches. Manganese (Mn) is one of the most popular element applied in Cu dopping. Mn could diffuse through the Cu interconnects and segregate along the interface between Cu and low-k dielectric layer. It was served as the barrier layer, adhesion promoter and oxidation retardant because the diffusivity of Mn in Cu was much faster than self-diffusivity of Cu, approximately one order of magnitude higher. It indicated that Mn atoms initially alloyed in Cu were migrated into surface and interface, and formed an oxide layer leaving the pure Cu behind after annealing step. In addition, Mn could also repair discontinuous barrier layer (Ta/TaN) by forming a local manganese silicate diffusion barrier layer. It was so called self-forming Cu-Mn diffusion barriers [13,14].
In this research, both Cu/1% Mn and Cu/1% Al served as underlying alloys were evaluated by Cu recess. The introduction of Cu/1% Al in the test was for the purpose of comparison. The main body of Cu interconnection of dual-damascene process included via etching, post etching wet clean, deposition of barrier films and Cu-seed layer and ECP. They were separated by different key process variables, such as dry etching power split, post etching as well as wet clean discharging gas flow rate split. The effect of these process variables on Cu loss under via bottom was evaluated in the experiment.
FIGURE 2 illustrated a schematic diagram of Cu recess in the device. The Cu recess of via bottom was observed using the step-by-step TEM followed by dry etch and wet clean processes. The Cu line was receded back into the bottom of Cu metal after the process. The Cu recess data were helpful to define which stage played the crucial role in Cu loss of via bottom. Electrical and wafer yield tests were applied in order to locate any abnormality after all processes were completed.
To unveil the effects of thermal/electronic stresses on Cu voids under via bottom, HTS (175oC) and HTOL (175oC with double device operation voltages) were performed to evaluate wafer yield swap after HTS and HTOL. Wafer yield swap was able to exam the yield before/after HTS and HTOL. The good die was failed if the Cu loss under via bottom occurred. After wafer yield swap dice was confirmed, failure analysis was performed by focus ion beam (FIB), scanning electron microscope (SEM) and transmission electron microscope (TEM). In addition, the chemical analysis was examined using energy dispersive spectroscope (EDS).
Results and discussion
A special design of metal line via structure with high aspect ratio of approximately 5 was performed in order to deteriorate Cu loss under via bottom. We inspected Cu recess of two different underlying metals, Cu/1% Mn and Cu/1% Al. FIGURE 3 displayed Cu recesses of Cu/1% Al and Cu/1% Mn underlying metals, respectively. Under the same process condition, the Cu recess of Cu/1% Mn was only half of Cu/1% Al, so Cu/1% Mn was more protective than Cu/1% Al. There was a strong correlation between EM cumulative failure rate and the type of underlying metals. Cu/1% Al showed much lower time to failure (TTF) and deteriorated EM performance as compared with that of Cu/1% Mn. It clearly demonstrated that Cu/1% Mn was more protective than Cu/1% Al, and failure rate of Cu/1% Mn was only 1/30 of Cu/1%. The performance of Cu/1% Al was significantly inferior to that of Cu/1% Mn. Therefore, Cu/1% Al was selected in following tests in order to enhance the differences of other key process variables.
In the standard (STD) condition, Cu recess was inspected by step-by-step TEM of dry etching and post etching wet clean with discharging gas process, and there were approximately 5nm and 7nm (12nm–5nm=7nm)in depth of Cu loss as shown in FIGURE 4. The following barrier films and Cu-seed process only slightly consumed underlying Cu. The Cu recess only slightly increased 0.3 nm in barrier film deposition process. The pre-cleaning process was necessary before barrier film deposition in order to remove CuO on Cu surface for improved adhesion. Based on observations of Cu recess results in step-by-step TEM, post etching wet clean process also played an important role in Cu recess of via bottom.
Dry etching by plasma not only eroded about 5nm in depth of Cu under the via bottom but also oxidized the underlying Cu which was supposed to be removed in subsequent wet cleaning process. Post etching wet clean included applying chemical solvent to clean by-product of dry etching and DI water clean to remove the chemical solvent. The DI water was with aid of discharging gas, such as CO2, in order to neutralize the accumulated charge generated by the plasma in previous dry etching. However, the discharging gas acidified the DI water and resulted in Cu loss in post etching wet cleaning process.
FIGURE 5 shows Cu recesses with different dry etching power splits. The change of plasma power split changed the degree of Cu recess. At the condition of 200 W less than STD, i.e., STD-200W, the Cu recess was less than 3nm. Although the structure looks good in shape, poor performance was observed from electrical test and wafer yield after the process was completed. Via open resulted in upper Cu disconnected from underlying Cu as demonstrated by TEM observation (Fig. 5). It was deduced that dry etching process did not etch entire via hole, especially for the dielectric layer. Although post wet cleaning slightly extended the open area under via bottom, barrier films were not well deposited on the via hole. Therefore, poor coating was obtained from the subsequent ECP process. The via resistance marked up significantly as the dry etching power decreased to 200 W less than STD, i.e., STD-200W.
FIGURE 6 shows wafer yields after open/short tests with different dry etching power splits. In the open/short tests, the failure rate was decreased with decreasing the dry etching power from STD+100W to STD-100W due to less damage to the Cu substrate for lower dry etching power. The Cu recess was decreased from 17.9 nm (STD+100W) to 8.7 nm (STD-100W) as demonstrated in FIGURE 5. However, dramatically increased failure rate was observed when the dry etching power was decreased to 200 W less than STD (STD-200 W). Because the lowest dry etching power, STD-200W, was insufficient to enlarge the via hole, and resulted in increasing the via resistance. Therefore, the failure rate of STD-200W was as high as 10% as displayed in Fig. 6. There was an optimal dry etching power of STD-100W in order to maximize the wafer yield in the experiment.
FIGURE 7 showed the variation of Cu recess with different discharging gas flow splits in the post etching wet cleaning process. The discharging gas flow was strongly related to the Cu recess, and it demonstrated that the chemical property of wet clean also played a crucial role in Cu recess. FIGURE 8 showed that the wafer yield failure rate was decreased with decreasing the post wet clean discharging flow from STD+200 sccm to STD-400 sccm. The major function of discharging gas, CO2, neutralized the accumulated charge generated by the plasma in previous dry etching. It was necessary in post etching wet cleaning process. However,it should be kept below STD-300sccm in order to improve wafer yield in the experiment.
The reliability test result of HTOL with thermal and electronic stresses over 168 hours showed several good chips transferred to bad ones with open short bin, which was called bin swap. FIB, SEM, TEM and EDS were used in failure analyses. FIGURE 9 showed the comparison of Cu recesses before and after HTOL tests for 168 hours. It was obvious that a deeper Cu recess was observed after stress applied. Before the stress applied, the via interconnect linked with underlying metal line. This is the key reason why it was difficult to detect this type of failure in the electrical test. In Fig. 9, the Cu recess before stress applied was 23.3 nm and it extended into 42.4 nm after HTOL test for 168 hours. The Cu recess extended into twice or even triple after thermal and electronic stresses applied. Therefore, quality of the via bottom joint was greatly deteriorated if there were Cu voids under the via bottom. With increasing applied thermal and electrical stresses to via bottom, the crack propagated to entire via bottom. The via bottom finally was disconnected from underlying metal line. It was so-called via open in semiconductor industry.
FIGURE 10 showed TEM bright field and EDS mapping of Ta at the failure location after HTOL for 168 hours. Taking a close look at the via bottom next to the interface of underlying metal line, the non-uniform barrier film was widely observed as shown in Fig. 10(a). It was the original failure location. In Fig. 10(a), TEM inspection of the failure location after HTOL test for 168 hours showed significant Cu loss, more than 30 nm, under via bottom. It was much greater than the Cu recess before thermal and electrical stress applied (12 nm). Based on the EDS mapping of Ta (Fig. 10(b)), the barrier film, TaN, was formed adjacent to the Cu loss of via bottom. It was important to note that the TaN was almost disappeared from corner of the via bottom. The disconnection of barrier film from the corner resulted in deteriorated Cu interface, and the Cu began to degen- erate and shrink under applied thermal and electronic stresses. It finally resulted in separation of the upper and underlying Cu. The via bottom was completely opened and caused the failure of device.
With the metal line dimensional shrinkage in advanced packaging, Cu metallization has increased the concerns on long-term reliability of devices caused by Cu loss under via bottom. This work explores the effect of underlying metallic alloys and the influence of Cu loss under via bottom after dry etching and wet clean. Important conclusions are listed below:
1. Cu/1% Mn is more protective than original Cu/1% Al. The application of Cu/1% Mn improves both EM and SM resistances of via bottom.
2. Both plasma power of dry etching and the discharging gas flow of wet clean play important roles in the Cu loss under via bottom. Cu loss was initiated first after dry etching due to plasma damage. The plasma not only etched the underlying Cu of via bottom, but also oxidized the underlying Cu surface. Subsequent post etching wet clean with acidic water generated by discharging gas removes CuO at interface, and causes more Cu loss in subsequent wet cleaning process. They are the major mechanism of Cu loss under via bottom. Pre-cleaning of barrier films to remove superficial CuO on Cu for better adhesion is only a minor factor in Cu loss under via bottom.
3. To Improve the Cu loss under via bottom, effective approaches include applying protective metal line, such as Cu/ 1% Mn, minimizing interfacial damage by decreasing the power of dry etching, and the discharge gas flow of post etching.
Authors greatly acknowledge the support of Taiwan Semiconductor Manufacturing Company (TSMC) for this study.
1. K.Ueno, M.Suzuki, A.Matsumoto, K.Motoyama, T.Tonegawa, N. Ito, K. Arita, Y. Tsuchiya, T. Wake, A. Kubo, K. Sugai, N. Oda, H. Miyamoto, S. Satio, “A high reliability copper dual-damascene interconnection with direct-contact via structure”, 2000 IEDM Tech. Digest IEEE (2000), p. 265.
2. M.H.Tsai,W.J.Tsai,S.L.Shue,C.H.Yu,M.S.Liang,“Reliabilityof dual damascene Cu metallization”, in: Proceedings of the 2000 Inter- national Interconnect Technology Conference, IEEE (2000), p. 214.
3. C.Ryu,K.W.Kwon,A.L.S.Loke,H.Lee,T.Nogami,V.M.Dubin,R.A. Kavari, G.W. Ray, S.S. Wong, “Microstructure and reliability of copper interconnects”, IEEE Trans. Electron Devices 46 (1999), p. 1113.
4. M.H. Tsai, R. Augur, V. Blaschke, R.H. Havemann, E.F. Ogawa, P.S. Ho, W.K. Yeh, S.L. Shue, C.H Yu, M.S. Liang, “Electromigration reliability of dual damascene Cu/CVD SiOC interconnects”, in: Proceedings of the 2001 International Interconnect Technology Conference, IEEE (2001).
5. J.P. Lu, L. Chen, D. Gonzalez, H.L. Guo, D.J. Rose, M. Marudachalam, W.U. Hsu, H.Y. Liu, F. Cataldi, B. Chatterjee, P.B. Smith, P. Holverson, R.L. Guldi, N.M. Russell, G. Shinn, S. Zuhoski, J.D. Luttmer, “Understanding and eliminating defects in electroplated Cu films”, in: Interconnect Technology Conference, Proceedings of the IEEE 2001 International (2001), p. 280.
6. Z.G. Song, S.K. Loh, M. Gunawardana, C.K. Oh, S. Redkar, “Unique defects and analyses with copper damascene process for multilevel metallization”, in: IPFA 2003, Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, (2003), p. 12.
7. P. Wrschka, J. Hernandez, G.S. Oehrlein, J.A. Negrych, G. Haag, P. Rau, J.E. Currie, “Development of a slurry employing a unique silica abrasive for the CMP of Cu damascene structures”, J. Electrochem. Soc. 148 (2001), p. 321.
8. T.C. Wang, Y.L. Wang, T.E. Hsieh, S.C. Chang, Y.L. Cheng, “Copper voids improvement for copper dual damascene interconnection process”, J. Phy. Chem. Sol. 69 (2008), p. 566.
9. R.L. Guldi, J.B. Shaw, J. Ritchison, S. Oestreich, K. Davis, R. Fiordalice, “Characterization of copper voids in dual damascene processes”, in: Proceedings of Advanced Semiconductor Manufac- turing 2002 IEEE/SEMI Conference and Workshop (2002), p. 351.
10. J. Reid, V. Bhaskaran, R. Contolini, E. Patton, R. Jackson, E. Broadbent, T. Walsh, S. Mayer, R. Schetty, J. Martin, M. Toben, S. Menard, “Optimization of damascene feature fill for copper electro- plating process”, in: Proceedings of Interconnect Technology, IEEE International Conference (1999), p. 284.
11. G.B. Alers, D. Dornisch, J. Siri, K. Kattige, L. Tam, E. Broadbent, G.W. Ray, “Trade-off between reliability and post-CMP defects during recrystallization anneal for copper damascene interconnects”, in: Reliability Physics Symposium, 2001. Proceedings of the 39th Annual 2001 IEEE International (2001), p. 350.
12. T.C. Wang, T.E. Hsieh, M.T. Wang, D.S. Su, C.H. Chang, Y.L. Wang, J.Y.M. Lee, “Stress migration and electromigration improvement for copper dual damascene interconnection”, J. Electrochem. Soc. 152 (2005), p. 45.
13. J. Koike, M. Haneda, J. Iijima, M. Wada, “Cu alloy metallization for self-forming barrier process”, IEEE Interconnect Technology Conference (2006), p. 161.
14. J. Koike, M. Wada, “Self-forming diffusion barrier layer in Cu-Mn alloy metallization”, App. Phy. Lett. 87, 041911 (2005)
15. J.P. Wang, Y.K. Su, “Effects of surface cleaning on stressvoiding and electromigration of Cu-damascene interconnection”, Trans. Device. Mater. Relia. IEEE (2008), p. 210.