IFTLE 6 Copper-Copper and IMC Bonding

By Garrou
.............before we begin I wanted to let you know that the PFTLE web page is now up at http://www.pftle.net/. Go there and look around. All of the 128 previous blogs are now accessable, printable and searchable. More on that in the next blog................

Metal-metal bonding at the 2010 ECTC

A few weeks ago I promised to eventually bring you back to more detail on all the copper bonding studies presented at the 2010 ECTC. The categories I will include here are thermocompression Cu-Cu bonding, direct Cu bonding and IMC (intermetallic compound) formation (usually Cu-Sn-Cu bonding).

M-M direct bonding continues to be of significant interest since it is known that it is scalable as evidenced by the SOITEC SOI process which has been in mass production for a decade.

Research Triangle Institute detailed their study on IMC (Cu-Sn-Cu) bonding and Cu-Cu thermocompression bonding. Cu/Sn and Cu strata ready to be mated are shown in the fig below.

The RTI group is comfortable with 20 um pitch features. Anything below that and they saw slippage and subsequent misalignment when the interfaces were brought into contact. (It is felt that this is an equipment limitation not a technology limitation.) Author Reed commented that the plating of 5 um pillars “..requires very good control of the grain structure of the Sn” The Sn surface was flattened using an in situ coining process at 40 Kgf. The copper surface roughness they achieved for various processes is compared in the Table below.

Bonding was performed under a pressure of 5X10ee6 kg/msq for 3 min at 275 to 300 ₀C. Intermetallic phases at the bondline were identified by EDS as Cu3Sn. There was no Cu6Sn5 or unreacted Sn in the bond.
The Cu/Sn-Cu devices with underfill were subjected to 100 thermal cycles (+125°C to -40°C), re-probed, and then 100 hours of 85% RH / 85°C stress testing and re-probed. There were no significant changes in the electrical yield or channel resistance after thermal cycling. The average resistance was 156 Ω before and after stress testing.
Cu-Cu bonding was performed similarly at 325 ₀C and a pressure of 32.2 Kgf for 15 min. The Cu-Cu process was sensitive to any Cu dishing during the CMP with corner and edge pillars showing the most impact. During the bonding process CuO formed on the exposed Cu surfaced in the gap. Chains gave a resistance of 95.9 mΩ.
Die shear strength for both samples was ~ 8kg. For this die size, the 1x shear strength specified in MILSTD- 883E is 2.5kg. Failure occurred at the bond interface


Samsung is one of the companies we are following closest in roder to determine the commercial progress of 3D IC. [ see PFTLE: PFTLE 122 "3-D IC at the IEEE ISSCC", 3/12/2010 and PFTLE 116 "Samsung 3-D IC Roadmap" , 02/01/2010]. At the 2010 ECTC, Samsung reported on their studies to determine the best Cu/Sn D2W (die to wafer) bonding approaches. Their test vehicle is shown in the figure below. The pads on the bottom die were Ni/Au rather than Cu. Pads are on 40 um pitch.

They examined 4 bonding schemes: (1) thermocompression (TC) with profiled heating on the bond tool and bond stage; (2) TC with constant heating on the bond tool and bond stage ; (3) fluxless local reflow bonding ( microscrubbing) and (4) flux bonding.

For TC bonding they found that bump height uniformity, TTV (total thickness variation) and wafer warpage played an important role.

1. TC Profiled heating (i.e. keeping the bonding head <>


The IBM group notes that Cu-Cu bonding is preferred due to low resistance and superior heart conduction but that high temperature and high co-planarity are needed and that there are alignment problems due to shifts caused by thermal expansion during the joining of these very small features.


Nanyang Univ continues to study the use of a self assembled monolayer, SAM (i-hexanethiol) to protect copper surfaces during the Cu-Cu bonding process [ see PFTLE 103 "Show Me the Copper !", 10/23/2009 ]. Upon absorption of the SAM, the Cu surface roughness is reduces from 1.96 nm to 1.55 nm. The SAM can be desorbed from the Cu surface at ~ 200 C. While there is evidence that there is indeed Cu grain growth when samples are bonded at 250 C (vs the control without SAM) the process does not yet look ready for prime time. Unless such a process significantly decreases the surface roughness requirements of TC bonding, one appears better of using a direct bonding process.


IMEC reported on their thermo-compression Cu-Cu bonding process for their standard Cu nails process.

The 5um diameter TSVs are etched through the PMD. A thick Ozone-TEOS SiO2 liner is conformally deposited in the TSV holes in order to isolate the TSVs from the Si bulk and to reduce the capacitive coupling. The TSVs are filled with Cu by plating and the Cu overburden is removed by CMP. Finally before final passivation, a Cu layer is added in order to connect the TSVs to the BEOL interconnect. Subsequently the wafer is mounted on a temporary carrier and thinned down to a Si-thickness of ~25 μm by a combination of grinding and CMP. At the end of this sequence, the copper of the TSVs is exposed on the wafer backside. Next the Si is recessed ~700nm by dry etching the Si with respect to the copper TSV. The result of this process is the 10μm pitch Cu nails structure shown in the figure.

In conventional Cu Back-end technologies this anneal is introduced after CMP in order to soften the Cu (through recrystallization) and thus reduce the CMP time and slurry consumption to remove the Cu overburden. However, due to the large relative dimensions of TSV, built up stress causes large Cu hillock growth from Cu TSV during the anneal at 420ºC after CMP. These protrusions are a potential threat to the IC interconnects layer, especially in case of low-k integration. This copper pumping has been discussed previously [ see PFTLE 103 "Show Me the Copper ! ", 10/23/2009 and PFTLE 125 "3D IC at Ft McDowell", 03/27/2010]

IMEC has shown that CMP of these extrusions after 20 min at 420 ◦C (in forming gas) anneal, will eliminate the protrusions from forming again during any subsequent anneals or high temperature processes.

During the Si recess process IMEC warns that Si etching with SF6 or SF6/O2 results in a highly corroded Cu surface (the protruding nail head). Addition of CF4 was necessary to achieve an acceptable Cu surface. This Cu must then be passivated (i.e Arch MS6020) in order to avoid oxidation during the thermo-compression process.

IMEC also provided further details on their Cu/Sn IMC bonding process. IMEC draws a distinction between processing done above (termed TLP) or below (termed SMB) the melting point of the Sn. When it comes to pressure (compression) requirements, TLP requires far less pressure since the molten Sn makes up for surface irregularities whereas the SMB requires higher pressure . The average roughness of their Cu and Sn plated bumps are 200 and 500 nm respectively. Peak-to valley measurements are even more revealing ( 900 and 2000 nm respectively). The rough bumps prevent Cu and Sn from having good contact and the subsequent inter-metallic formation. Therefore, bonding pressure becomes an important parameter. In fact there is a lower-limit pressure of about 20 MPa below that there is electrical connection lost. However, 150 MPa is almost the upper limit beyond which too much Sn
squeezes out leading to electrical short. Therefore, IMEC chose 50 MPa as a baseline process.

When it comes to pad cleaning NUF (no flow underfill with fluxing additives) was found to work best

CEA Leti

Lea Di Cioccio and her co-workers at CEA Leti continue reporting on their Cu-Cu direct bonding studies [ see PFTLE 58 "Fisk, Buckner and Pasta on the North End", 12/31/2008 and PFTLE 26 "3D Practitioners Assemble at Ft McDowell", 03/23/2008]
They define direct bonding as a process by which two mirror-polished wafers are put into contact and held together at room temperature by adhesive forces, without any additional materials.

Using test vehicles devised at NIST, their extensive electrical measurements show that the direct bonding has negligible effect on the electrical resistance of the structures they have fabricated. Daisy chains of hundreds to tens of thousands of connections were tested and showed a resistance of 79.5 milli ohm per node (bonding interface + copper lines) and a specific contact resistance of the bond ~ 22.5 milli ohm / um sq was extracted.

Their detailed study of the Cu-Cu direct bonded interface reveals a 4 nm CuO interfacial layer which begins to coalesce after 2 hrs anneal at 200 ◦C where CuO is known to become thermodynamically unstable. After a 2 hr 400 ◦C anneal the bonding interface has materials properties very close to native copper.

After a 2 hr 200 ◦C post bonding anneal bonding energy is found to be 1.14 J/m2 which is strong enough to sustain post bonding processing such as thinning. After 2 hrs at 400 ◦C a bond energy of 6.6 J/m2 was measured.

The Leti group has also examined the possibility of tungsten-tungsten direct bonding . As deposited by CVD, the W surface roughness is measured at 20 nm which is unacceptable for direct bonding. W CMP was able to bring the RMS roughness down to 0.4 nm. However, W-W bond energy , measured after 2 hr anneals at various temperatures showed very weak bonding had occurred as shown in the fig below. Even at 800 ◦C the bond energy has only reached 1.5 J/m2. Clearly this process is not yet as effective as the Cu-Cu direct bonding process.


- I'll be at Semicon next week gathering new information for you
Tues June 13th AM I'll be on the panel at TechXSPOT "Bridging the Gap"
Tues June 13th PM I'll be at the Suss workshop "3D Bonding and Thin Wafer Handling"
Wed June 14th PM I'll be at the Alchimer workshop "TSV Metallization that Cost 80% Less"
Hope to see a lot of you at the Sematech reception on Wed night.

For all the latest on 3-D IC and advanced packaging stay linked to Insights From the Leading Edge, IFTLE……..

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