IFTLE 77: MEPTEC 2.5, 3D and beyond

By Garrou
Last week in Silicon Valley MEPTEC and Semi held the "2.5D, 3D and Beyond Bringing 3D Integration to the Packaging Mainstream" Conference.

Zeki Celik, principal engineer in the package design and characterization group at LSI , looked at the thermal characterization of various 2.5 and 3D package configurations. Option 3, where the logic die is not heat sinked to the lid, results in the overall highest TJ, max . Option 2, where the silicon interposer is between the memory and the logic die, can be heat sinked to the lid lowers the overall temperature, but equilibrates the temperature of the memory to the temp of the logic. Option 1, which is the silicon MCM-D option, is the overall best solution with the lowest memory temperature.

Marnie Mattei, senior director of TSV product development at Amkor Technology, examined assembly strategies for interposed products. Primary drivers for interposers, which are now pretty much stansdardized at 100μm thick, are shown below.

Product challenges include:

Die-die / Die-substrate joining
- Micro bump uniformity; method of join; materials

Die-die X-Y spacing
- Fillet sizes and pad metallurgy
- Process assy sequence; micro-join method & materials

Thermal / power management
- Use of lids, stiffeners & passives
- Underfill/resin bleed, adhesive compatibility
- Process assy sequence; micro-join method & materials

Warpage control
- Interposer warpage; substrate warpage
- Top die warpage -- top die area density/distribution

Intermediate e-test points
- Process assembly sequence

Available assembly flows in Amkor include:

[tc=thermocompression, NCP=non conductive paste (preapplied underfill); CUF capillary underfill]

Sunil Patel, director of GlobalFoundries' customer package technology group, looked at backside integration and global supply chain challenges for 2.5 and 3D. He sees some application segregation as follows:

GF's perspective on supply chain options mimics many others, namely foundry-centric, OSAT-centric, and 3rd party-centric.

Although GF pointed towards many collaborations with customers, OSATs and institutes, no indication was given as to when and how to expect GF to begin volume manufacturing of 2.5 or 3D products. While others have recently proposed that GF manufacturing is imminent, IFTLE does not see this happening just yet; they are probably still a year or two away.

Subramanian S. Iyer is an IBM Fellow and chief technologist at the microelectronics division within IBM Systems & Technology Group, responsible for technology strategy and competitiveness, and functionally for embedded memory and three-dimensional integration. His presentation focused on prospects for 2.5 & 3D integration. Among his main messages:

- Scaling is getting more difficult and expensive and yielding less;
- Bandwidth and latency are at a premium;
- Power management, delivery, distribution, and dissipation are significant;
- Integrating large amounts of low latency memory is a major challenge for modern multi-core processor design;
- 3D achieves high performance and low power (AC); and
- Supply chain management will be the toughest nut to crack

Repeating a theme that Subu has shared at previous conferences, he showed the cross-section of an 11-level-metal, 32nm chip (below) to make the point that due to size miss match, sometimes vias-middle TSV must be connected at upper levels of metal and not at the lowest level as we usually draw them in our cartoons.

For all the latest in 3DIC and advanced packaging stay linked to IFTLE......................


Dr. Phil Garrou gives his insight into leading edge developments in 3-D integration and advanced packaging, reporting the latest technical goings on from conferences, conversations, and more.

Previous Posts

IFTLE 156 2013 ConFab part 1 Sony, IBM, TI, SCP

Sun Jul 28 09:33:00 CDT 2013

IFTLE 155 2013 IEEE ECTC Part 2 Temporary Bonding

Sun Jul 21 11:54:00 CDT 2013

IFTLE 154 ICEP part 2: Thinning Effects on DRAM memory retention and More

Thu Jul 11 15:51:00 CDT 2013

IFTLE 153 IMAPS DPC part 3 Leti, Dow, STATSChipPAC

Wed Jul 03 16:25:00 CDT 2013

IFTLE 152 2013 IMAPS Device Packaging Conference part 2

Sat Jun 22 16:04:00 CDT 2013

IFTLE 151 2013 IMAPS Device Packaging Conf part 1 - Amkor

Sun Jun 16 11:30:00 CDT 2013

IFTLE 150 ICEP Osaka part 1

Mon Jun 10 10:22:00 CDT 2013

IFTLE 149 2013 ECTC part 1

Tue Jun 04 09:45:00 CDT 2013

IFTLE 148 The Future of Packaging: A Look From 50,000 Feet

Sat May 25 11:36:00 CDT 2013

IFTLE 147 IME Updates 2.5D; Qualcomm Updates 2.5 / 3DIC at ICEP

Mon May 13 10:16:00 CDT 2013

IFTLE 146 TSMC Apple Rumors; Gartner OSAT Mkt Numbers; Novati

Sat May 04 12:01:00 CDT 2013

IFTLE 145 GPU Roadmap, IEEE 3DIC back in SF; ConFab 2013 Pkging

Sun Apr 28 15:23:00 CDT 2013

IFTLE 144 Personnel Changes in Taiwan; Glass Usage in WLP

Sun Apr 21 10:29:00 CDT 2013

IFTLE 143 HMC status; Pkging Materials $$ now Exceed Wafer Fab Materials

Sat Apr 13 17:15:00 CDT 2013

IFTLE 142 GlobalFoundries 2.5 / 3D at 20nm; Intel Haswell GT3; UMC / SCP Prototype Details

Tue Apr 09 16:59:00 CDT 2013

© 2013. PennWell Corporation. All Rights Reserved. PRIVACY POLICY | TERMS AND CONDITIONS