Insights From Leading Edge

IFTLE 82 3DIC at the 2011 IEEE IEDM and other 3D and Adv Pkging topics

My Christmas and New Years time off was great; hope yours was too. Hannah and Madeline got their letters of to Santa and I had a great Texas Christmas with the grandaughters.

…and now back to 2011 conference coverage…

2011 IEDM

3DIC presentations at the recent IEEE IEDM Conference focused on potential reliability concerns.

ST Micro / Leti reported on two potential reliability issues for direct bond copper — namely stress induced voiding and electromigration. Electromigration (EM) and stress-induced voiding (SIV) testing was performed on bonded daisy chains to investigate the reliability of the structures. Test vehicles were wafers bonded at room temperature, atmospheric pressure, and ambient air and then annealed at 200°C or 400°C to strengthen the bonding.

In some NIST-type devices, they observed voids at the cathode side and copper extrusion next to the anode pads after 200°C post-bonding anneal and exposure to 325°-350°C and 3-3.5 MA/cm2. Time-to-failure (TTF) is defined as a 10% resistance variation. They make arguments to support the conclusion that the Cu-TiN interface appears to be the dominant pathway for EM — not the Cu-Cu bonded interface as might be expected. On some tested die they observed voids and copper extrusion on both opposite sides of the daisy chain showing that the structure acts as one continuous interconnect without interface separation between copper lines on the two bonded levels. In standard copper interconnects and vias chains, each copper line is separated by the metallic barrier between the line and the vias.

SIV testing of the daisy chains interconnected by direct copper bonding process after 400°C anneal and thermal stressing at 175°C-200°C and a current of 1mA for 2000hrs showed no degradation, i.e. less than 5% resistance change for all the tested samples.

They conclude that: "Direct copper bonding does not impact on the failure mechanisms concerning Cu interconnect reliability."

Koyanagi-san and his group at Tohoku University reported on their studies on W / Cu hybrid TSVs. They propose that high-density 3D-LSI die requires more than 104-105 μbumps and TSVs per chip and die thickness of <10μm with near zero remnant stress. Due to this, W TSVs may outperform Cu TSVs not only due to their ability to form sub-micron vias, but also since W does not diffuse in silicon the way Cu does, and leaves very minimum stress in active Si owing to smaller difference in CTE between W and Si. Therefore, W-TSV is preferable for high-density and high-speed TSVs with small diameter and small capacitance for signal lines.

However, W-TSV is not as suitable for power/ground (GND) lines because of its higher resistance. Cu-TSV with larger diameter and lower resistance should be employed for TSVs for power/GND lines. Cu-TSVs with larger diameter are also more preferable to suppress Cu diffusion since a barrier metal such as Ta can be conformally and uniformly formed into deep trench for TSV which effectively suppresses Cu diffusion. One can also suppress the influences of Cu diffusion on device characteristics by placing Cu-TSVs for power/GND lines apart from the active areas. Thus, the Tohoku group proposes a high-density 3D-LSI using W/Cu hybrid TSVs.

μ-Raman spectroscopy revealed that mechanical stresses increase with an increase in TSV diameter for both Cu- and W-TSV. They conclude that Cu-TSV with the size of <10μm and W-TSV with the size of <1μm leave only compressive stress in the TSV spacing region when the TSV pitch was smaller than twice of TSV size. It is important to increase the TSV pitch to larger than 2�? the TSV size to avoid peeling (inside the via), extrusion of the via metals, and cracking of the LSI die. Residual stress in thinned die changes from compressive stress for the die/wafer thickness of >100μm to tensile for thicknesses <30μm. They warn that "tensile stress leads to die-cracking due to weakening of Si-Si bond, which is a threatening issue in 3D-LSIs."

Farooq of IBM detailed their reliability studies (thermal cycling >500 cycles) and thermal stress (>275°C for 1500 hr) on 3D modules built by integrating Cu TSVs with high-k/metal gate and embedded DRAM.

They found no degradation of TSV or BEOL structures, and show that there is no significant impact on device characteristics from TSV processing and/or proximity.

TSVs were integrated at fatwire (upper metal) levels to optimize wire-ability and process complexity with 4 to 12 metal levels including low-k interlevel dielectric (ILD), built on SOI and bulk Si wafers. TSV of <100μm depth were etched with near vertical sidewalls at a minimum pitch of 50μm. An example of this is shown below.

TSV and BEOL structures did not degrade after 500 thermal cycles (-65°C-150°C), and no change in either the leakage or the wiring resistance was observed. Structures consisting of wiring and via chains above and near the TSV also showed no degradation after thermal cycling. Wafers baked at 175°C-275°C for 1500hrs showed no voiding or delamination occurred near TSVs. Frontside and backside wiring levels on a thinned wafer were connected with TSVs to create chains of 3000 links; the chains showed no change in resistance after 500 thermal cycles.

TSV insulator breakdown voltages of 250V-300V were observed.

They observed that significant shifts in device characteristics were possible for some processing conditions, in particular "FET Vt was shifted under certain etch conditions" but optimizing the etch process minimized this impact. In general, they concluded: "With optimized design and processing, stress fields associated with TSVs are significantly lower than those required for strain engineering of the devices, and are not expected to shift device characteristics."

More detail is available here [link].

Honeywell and Tezzaron to build rad hard 3D-ICs

Honeywell Microelectronics and Tezzaron Semiconductor have announced that they will be working together to produce radiation-hardened 3D integrated circuits. Honeywell’s S150 process will use Tezzaron’s 3D stacking to greatly increase circuit density without migrating to a smaller node. The resulting three-dimensional integrated circuits (3D-ICs) are also expected to use much less power than their 2D counterparts. Tezzaron CTO Bob Patti commented: "Memory can now be integrated vertically rather than embedded in the logic die. The current practical limit is around 32 Megabits, but 3D could put as much as 4 Gigabits of high-quality DRAM onto a single rad hard chip."

Tezzaron also announced a research collaboration agreement with the A*STAR Institute of Microelectronics (IME). The two organizations will improve and refine the design and manufacture of silicon interposers and work to standardize the process, flows, and process design kits (PDKs). Initial early production devices are already in development, based on IME’s TSI (through silicon interposer) technology and incorporating 3D-ICs from Tezzaron. Fabrication will be completed in IME’s state-of-the-art 300mm R&D fab. The resulting TSI technology from the collaboration will form the foundation for the TSI Consortium driven by IME, to be launched in early 2012.

IME and Tezzaron have a history of cooperation dating back to 2001, when IME provided its copper line technologies to Tezzaron for their wafer stacking endeavors.

LED testing update

We are now 4+ months into our lightbulb testing and I am happy to report that both bulbs (LED and CFL) continue to burn bright — as well they should, since you will recall the average life of an incandescent is ~1 year. [ see IFTLE 63, "Bidding adieu to Lester Lightbulb."

I have come across an interesting article which tries to explain the new light bulb test protocols and adds to what I tried to explain [link].

The winner of the contest will be announced next week — along with the answers to who all those people were!

For all the latest in 3DIC technology and advanced packaging stay linked to IFTLE……….


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