Insights From Leading Edge

IFTLE 90 Highlights from the IEEE 3DIC 2012 Japan

The 2011 IEEE 3DIC Conference scheduled for Japan, as most of you know, was postponed due to the earthquake and Tsunami issues Japan experienced last year. The good news is that the conference which was postponed till Feb 2012 was held a few weeks ago and was a huge success. More than 250 attendees shared 32 presentations and more than 65 posters concerning the latest breakthroughs in 3D stacking technology.

In the next two blogs we will review what IFTLE considers some of the more important presentations and posters.

Effect of Sidewall Roughness on Leakage Current

Fujitsu has looked at the effect of sidewall roughness on leakage current comparing Bosch etched TSV to ULVAC NLD etched TSV (discussed below). Bosch etched scallops were 72 nm deep and 280 nm long while the NLD etched TSV were ultra smooth. 500 nm of SiON insulator was deposited by low temp PECVD (150C) followed by PVD of 50 nm of TiN and 50 nm of TI to serve as Cu barriers followed by 200 nm of Cu seed.

Leakage current between TSV was measured after annealing for 5 min at from 200 to 400C. Leakage current of NLD is lower than the bosch etched TSV initially and is less than 100x smaller than Bosch after anneal at 400C. These results are correlated with cracking of the insulation layer and subsequent migration of copper. It appears as though sidewall roughness initiates crack growth. Since anneal at 400+ is recommended to reduce the effects of copper protrusion [see IFTLE 6 "Cu-Cu and IMC Bonding Studies at 2010 ECTC..."], it is recommended by IFTLE that such leakage current experiments be run when optimizing Cu anneal process during TSV fabrication to insure integrity of the barrier and insulation layers after processing.

(Click on any of the images below to enlarge them.)
Effect of Sidewall Roughness on Copper migration

Koyanagi and his co-workers examined the influence of copper contamination on device reliability and found that when Bosch scalloping is high, conformal deposition of the dielectric layer and barrier layer is difficult and increases the likelihood of Cu atom diffusion through the thinned barrier on the point of the scallop especially during the thermal temperatures reached during post process thermal anneal.

They fabricated Si trenches with 5 um diameter and 10 um depth with sidewall scalloping of 30 and 200 nm. 100 nm thick oxide and Ta barriers of 10 or 100 nm where deposited by sputtering. This was followed by a 200 nm thick copper seed.

Electrical results showed the 10 nm Ta barrier failed to resist Cu migraion for both the shallow and severe scallops.

ULVAC non Bosch scallop free TSV

The magnetic loop discharge plasma (NLD plasma) used by ULVAC can be used for silicon or oxide etching. The etch profile is controlled by the SF6/O2 ratio. Sidewall roughness of less than 15 nm is obtained.

IMEC and Suss Demonstrate Integration of ZoneBond Process

IMEC has demonstrated integration of the ZoneBond process on their Suss XBC300-LF temporary bond cluster and DB12T peel debonder. The Zone bond process has been described before [see IFTLE 61, "Suss 3D Workshop at Semicon West"]

The bonding material is coated on the wafers in 19.2 +/- 0.4 um thickness. Scanning acoustic microscopy shows that the bonding to a silicon carrier is void free.

After thinning and backside processing the bonded wafers are soaked for a few hours in the adhesive solvent and laminated onto a UV sensitive dicing tape. The carrier wafer is then "peeled" off the device wafer.

The remaining glue is then removed while the device wafer is held on the film frame. Devices are diced subsequent to cleaning.

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