Questions and answers on FD-SOI

By Pete Singer
A month or so ago, we implemented (without much fanfare) the ability to comment and rank articles on this site, and more easily use social media tools. I’d like to call your attention to one interesting exchange, and also invite you to start posting comments of your own.

In mid-December, we posted an article titled “STMicro: 28nm FD-SOI is ready for manufacturing ” which elicited an interesting comment and response. The story noted that ST’s "feature-complete and silicon-verified" 28nm planar FD-SOI Technology Platform, which is now open for preproduction from the Crolles 300mm manufacturing facility, encompasses a full set of foundation libraries (std-cells, memory generators, I/Os, AMS IPs, and high speed interfaces), and a design flow ideally suited for developing high-speed and energy-efficient devices. Measurements on a multi-core subsystem in an ST-Ericsson NovaThor ModAp platform revealed a maximum frequency exceeding 2.5Ghz and delivering 800 MHz at 0.6V, according to Jean-Marc Chery, EVP/GM, digital sector, and CTO/chief manufacturing officer of STMicroelectronics.

Sang Kim first commented, noting that “IBM had developed FD-SOI technology for the first time, but was not successful in manufacturing up to now because of the following four main reasons: Floating body effect, self-heating, ultra-thin SOI approximately 7nm required for 28nm node, and high SOI wafer costs.” Kim noted that STMicro didn’t mention how it has resolved these four problems.

In response, STMicro’s Giorgio Cesana, director of technology marketing, posted a follow-on comment that I thought was quite interesting. Here’s what he said:

“Thank you for those comprehensive questions. Responding gives us a chance to provide details of the advances of UTBB FD-SOI technology and remove any doubts you may still have about it.

1. Ultra-Thin Body and Buried Oxide (UTBB) FD-SOI technology is very different from Partially-Depleted technologies manufactured before. Those partially-depleted technologies were affected by floating-body effects where the body was subject to an uncontrolled charging/discharging that led transistor behavior to depend on the previous transitions –i.e. making them suffer from a kind of memory effect. In UTBB FD-SOI technology, hybridation lets us contact the body, so it is not left floating, overcoming the problems with PD-SOI technologies.

2. Self-heating is also a problem that exists with partially-depleted SOI technologies, where the buried oxide thickness (~150nm) was thermally isolating transistors from the substrate, leading to self-heating effects. UTBB FD-SOI technology offers two advantages to overcome this self-heating: The Buried Oxide (BOX) is extremely thin (only 25nm thick in 28nm technology), offering significantly less thermal resistance; The big diodes, the drift MOS, the vertical bipolar, some resistors… are all implemented on the “hybrid” bulk part, eliminating even the thin BOX below them.

3. Wafer thickness: The ST process specification is for wafers with 12nm thick silicon (+/- 5A). Process manufacturing then “uses” part of the silicon film for the manufacturing of the transistors, leading to a final 7nm film below the transistors.

4. Wafer costs: UTBB FD-SOI technology manufacturing uses up to 15% fewer steps vs. our bulk planar 28LP HKMG gate-first technology. This process simplification, by itself, is capable of totally compensating for the current substrate cost difference. Then, we expect in high volume production, UTBB FD-SOI die costs should be even better than bulk planar, with substrate-cost erosion and with UTBB FD-SOI improving electrical yield over bulk planar.

We hope these answers convince you, as they’ve convinced us, of the suitability of FD-SOI technology for sub30nm semiconductor manufacturing.”

Thanks for the comments, and stay tuned for more of FD-SOI.

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