By Dick James, Senior Technology Analyst, Chipworks
On the Monday afternoon at IEDM the key paper for me was the Intel/Micron talk on their 3D-NAND flash part (paper 3.3), which is currently sampling to customers. Samsung put their V-NAND flash on the market last year, but that uses charge-trap technology, whereas the Intel/Micron device has adapted conventional floating gate technology to the vertical direction.
This is the first-generation product, with 32 active tiers plus additional layers for dummy wordlines and source and drain select gates. A vertical channel surround-gate structure is used for the flash cells. The CMOS decoders and sense-amps are situated under the NAND flash array, which saves significantly on die area. It appears that this product will be a 256-Gb memory, or 384 Gb when the TLC version is introduced. Die size is 168.5 mm2, giving a bit density of 1.52 and 2.28 Gb/mm2 for the MLC and TLC devices.
The wordlines/control gates are horizontal polysilicon layers with an ONO inter-poly dielectric, and the floating gates are also polySi. The vertical channel and tunnel dielectric are formed in holes etched through a horizontal polySi/oxide stack.
The process is shown below; the cell hole is first etched through the wordline tiers, and then the control gate is recessed back and the inter-poly dielectric is formed. The floating gate is then deposited, and etched back to form an isolated floating gate in each cell; the tunnel-oxide is formed, and the polySi channel is deposited to line the hole in the stack.
An image of the full stack is shown on the right; I see 38 wordline layers, plus a thick polySi layer at top and bottom of the stack, presumably for the drain and source select transistors. There are two tungsten metal layers below the stack for the decoders and sense-amps, and also the wordline drivers; and it looks like the M3 bitline is also tungsten. There is another metal level above used for power busses and global interconnects, but we don’t know if that is copper or aluminum.
Putting the wordline drivers under the array is claimed to keep the wordlines short, but it raises some questions – how are the wordlines contacted from below? Do we have the sort of staircase at the ends of the wordlines that we saw in the Samsung V-NAND, and could it be inverted? (Can’t imagine that!)
The vertical channels contact what looks like a polySi sourceline at the base of the stack; it’s a bit clearer in this schematic:
While the NAND cells are floating gate cells, we can see that the source and drain select devices are single gate oxide transistors.
The larger size of the cell improves the performance since it has a higher cell capacitance – more electrons can be stored, and a better natural Vt distribution (~50%) is achieved. (Note that at 20nm planar, less than 10 electrons gave 100mv Vt shift!)
The cell geometry also means that the cell/cell interference is reduced – again, comparing to the 20nm planar chip;
We will see what the commercial part looks like when we get our hands on one, likely in the first few months of next year. Unfortunately there are no scale bars on any of the images, so we have no feel for what the actual dimensions are; though probably not too different from the Samsung, which is classed as a 40nm device.
There are actually not too many features in common with the Samsung chip – vertical stacking with 32 active layers, and that’s about it. Otherwise, charge-trap technology vs floating-gate; polySi wordlines vs tungsten; metallization below the stack, vs none; and maybe a completely different way of accessing the wordlines.
For now, we wait and see!