Archive for 2011

    IFTLE 71: 450mm announcements

    October 17, 2011 4:15 PM by Garrou
    Moving to 450mm has several advantages, the main being that the area is 2.25× larger. This obviously means that more chips can be cut from one wafer, and less material is lost at the edges. The last conversion process from 200mm to 300mm wafers began in 2000, creating price reductions of around 30%-40% per unit. The elite of the global semiconductor industry now plan to move to 450mm wafers where a cost gain of 25%-30% is hoped to be achieved.

    Although the initial goals from the triumvirate of Intel/Samsung and TSMC called for a 450mm pilot line to be ready in 2012 [link], it does look like things are finally getting off the ground.

    Intel, GlobalFoundries, IBM, TSMC, Samsung create 450mm initiative

    New York State has entered into agreements for $4.4 billion in investments over the next 5 years from Intel, IBM, GlobalFoundries, TSMC, and Samsung to create a 450mm consortium and manufacturing center there. Reportedly this will create close to 7000 jobs, 2500 of which would be high-tech. (Hopefully these reported job numbers are more realistic than what have been reported recently for "green jobs" and jobs created from the "stimulus.")

    The facilities will be located in CNSE (College for Nanoscale and Science Engineering) "Albany NanoTech," CNSE's Smart System Technology & Commercialization Center in Canandaigua, SUNY-Utica, and IBM sites in East Fishkill and Yorktown Heights. New York State will invest $400 million in CNSE in Albany over a 5-year period.

    The joint 450mm project will focus on transforming existing 300mm technology into the new 450mm technology. These technology developments "may facilitate the possibility of building a 450mm production line in New York state."


    Since 2006, the SEMATECH ISMI organization has been looking at the early stages of the 450mm transition, including developing standards for the wafers, automation, and getting agreement on the development of the 450mm processing tools. Last year, the entire ISMI organization moved to Albany, from Austin, and the state of New York invested an estimated $300 million in the 450mm program at ISMI. Intel headed up the ISMI 450mm program, and has been on point for many of the negotiations with the tool suppliers.

    The announcement of the Global 450 Consortium consolidates the 450mm effort into one consortium, with access to the new CNSE Fab West building now under construction at the CNSE campus.

    TSMC 450mm announcements

    Earlier in the year, TSMC reported that the problems with 450mm were not technical but rather economic [link]. Recently TSMC reiterated that a pilot line at Fab 12 Phase VI starting with 20nm process technology, would be timed around 2013/2014, and a production line set for Fab 15 following around 2015/2016 [link]. "The timing for the Albany 450mm line and the TSMC line [...] will coincide with each other, or be very close," the company claims.

    Intel 450mm announcements

    In late 2010 Intel announced that as par of a $6B-$8B investment, it was upgrading several US facilities with the ability to handle 450mm wafers. The Hillsboro, OR facility D1X is scheduled for 2013.

    Intel says it will make the Albany site its "450mm East Coast headquarters," implying their D1X fab on the West Coast, which was "built with 450mm in mind," could be beyond an initial pilot-line.

    IMEC announces 450mm

    Not to be outdone, IMEC's president/CEO Luc van den Hove laid out a timeline that begins in 2012 with 450mm wafer tool and metrology testing, 450mm process development between about 2013 and 2015, and advanced production starting in about 2016.

    Van den Hove proposed the early work covering early metrology, process elements, wafer characterizations of stain, uniformity, and performance will be done in IMEC's present 300mm wafer fab which is 450mm compatible. Phase Two which will require full process flow will require its own clean room which will probably require a significant extension of the existing pilot wafer fab at IMEC's Leuven site. He said IMEC was looking at various options to accomplish that since construction would be required to begin prior to 2015.

    Where does this leave Micron?

    Mark Durcan, president/COO of Micron, is on record as saying that they are not a big proponent for 450mm saying that Micron would have to ''re-tool'' the entire company to move to 450mm. He indicated that 450mm would have to prove a "2.5× cost advantage over 300mm" [link].

    Following the NY consortium announcement, Micron quickly announced an expansion of its Boise Idaho R&D center with plans to make the facility "450mm-compatible." [link]

    Where is End Game?

    According to roadmaps, the 2015 450mm pilot lines coincide with what is expected to be the 10nm node, and 2017-2019 could be 7nm or less. As we have stated before, it is unclear to IFTLE how many players will have the financial or technical wherewithal to continue to proceed with scaling technology to these levels.

    Having said that, it certainly looks like 450mm is moving forward for those with the financial capability. So those of us involved in the packaging segment of the industry should begin looking at what will be necessary to move packaging technology to 450mm.

    For all the latest on 3D IC Integration and advanced packaging stay linked to IFTLE........

    IFTLE 70 Highlights of the Semicon Taiwan Embeddded Substrates Forum

    October 8, 2011 11:02 AM by Garrou
    The 2011 Semicon Taiwan Embedded Substrate Forum "Bridging the Last Mile of Heterogeneous Integration" was chaired by Dr. Kuo-Ning Chiang, Professor, Director-Advanced Packaging Research Center, NTHU.

    One of the main messages from the forum is that embedding passives into package substrates is just beginning for applications ranging from consumer electronics to routers. Embedded active in substrate has seen few commercial implementations but it is thought will grow in importance with time.

    JISSO has defined "embedded substrate" as containing embedded active or passive components or passive functions that are fabricated as part of the substrate fabrication process.


    Jan Vardaman of TechSearch presented an overview of the embedded substrate market. Advantages of embedded components are:

    - Small form factor (reduced Z-height), enables reduced board thickness
    - Improved performance
    - Shorter electrical path, EMI reduction, integrated passives
    - Shielding advantages for RF components
    - Embedded die technologies appropriate for:
    - Lower value, high yielding die where high interconnect density is required on both sides of the substrate
    - RF modules where embedding tested die allows high density SMT on top

    There are still concerns about:

    - Patent issues
    - Handling thin die
    - Solder joint reliability of buried joints
    - Cost (embedded die cost vs. die in package mounted on board)
    - Concerns about liability
    - Test (how to test after embedding component?)
    - Inspection (how to inspect an embedded component?)

    Takayoshi Katahira of Nokia addressed embedded technology from the mobile device perspective.

    Embedding technology can either be face up:

    - Cavity cut-out
    - Component placement
    - Lamination
    - Laser drilling
    - Plating

    Or it can be face down, where the component is soldered in place and then buried. E-B2IT is seen as the leading technology of this kind.

    Since 3D eWLB and RCP fan out technologies enable the same merits as substrate-based embedding, these can also be called "active embedding." Nokia sees high IO active embedding into packaging substrate coming soon.

    Top-Bottom interconnection and top patterning enabling 3D assembly will be suitable for:

    - Standard memories with high-pin count
    - DDR2 Quad Channel or DDR3
    - WLCSPs
    - Passives

    Many passives are mounted on mainboard for smartphones. Capacitors tends to be used in the greatest numbers. Soldering embedded caps has a clear advantage in process cost.

    Bruce Su of ASE presented chip embedding as a technology evolution after bumping. ASE is developing "advanced Embedded Assembly Solution Integration" or aEASI as shown below:

    EASI currently has the following design rules:

    For all the latest on 3D IC integration and advanced packaging stay linked to IFTLE..........

    IFTLE 69 Cell Phones and Memory Consolidation

    October 2, 2011 11:40 AM by Garrou
    The cellphone continues to pull in the functionality of digital cameras, PDAs, GPS navigators, mobile TV and numerous other applications. It is quickly becoming thedominant market driver for virtually all of these functions.

    Earlier this summer market research firm Forward Concepts issued a report, "Cellular handset and chip markets '11: An in-depth analysis of cellphones and their chips," which indicates that cellular handset shipments grew 12% in 2010 to 1.5 billion units. It includes some interesting points that those in high end packaging should study carefully.

    As we know, smartphones are expected to grow at an accelerated rate (15.4%) to the 318M unit level this year. The report provides extensive forecasts for all handset types and virtually all cellphone chips through 2015. Though Samsung and Apple are growing faster, Nokia continues to be the leading handset vendor. Nokia's average handset selling price is among the lowest because of their huge share of the low-end markets in China, India and Africa. Nokia is still the largest vendor of smartphones, but Apple is catching up, as illustrated in the graph below:

    In terms of chip revenue coming from cellular handsets, Qualcomm remains the "big dog" with 23% of the market. If we include TI, Infineon and ST-Ericsson, we can account for more than 50% of the chip revenue in this market:

    From the chart below we see that the display, the baseband chip and the image sensor account for more than 50% of the component value:

    Predicting memory supplier consolidation

    Anyone following the goings-on in the 3D IC market space would have to agree that Elpida has been at the forefront of the technology [see IFTLE 67] Several of these 3D practitioners such as Elpida, Samsung, and Micron (Aptina) also are in the memory business. A recent article attributed to Bloomberg Business Week [link] proposes that memory chip-makers ProMOS Technologies, Powerchip Technology and Elpida Memory, "burdened by debt, losses and falling prices, are under increasing pressure to seek mergers or exit the industry."

    Reportedly, Elpida, which is $4.6B in debt, is "producing chips that sell for less than they cost to make." Micron, market leader Samsung, and Hynix Semiconductor are the only DRAM makers among the top eight generating a profit. DRAM makers as a group have lost 19% of their market value this year, according to Bloomberg, which quotes a financial analyst's doubts: "I find it difficult to believe they [Elpida] are going to survive this downturn [...] Consolidation is inevitable for survival in this industry."

    The Japanese government's interest in maintaining an on shore supply of memory chips might limit who can acquire Elpida. Toshiba is thought of as a logical choice if such a merger is required.

    According to recent announcements, Elpida Memory is considering cutting back production at its Hiroshima facility and sending more work to Taiwan partner Rexchip, its JV with Powerchip [see "Elpida shifting output to Taiwan, blames yen and ASPs]. Reports indicate up to 40% of Elpida's domestic capacity (50,000 wafer/month, 300mm wafers) could go to Rexchip would be producing the majority of Elpida's output. The Taiwan partner would produce commodity DRAM, while the Elpida Hiroshima plant would focus on memory for smartphones, according to the Nikkei daily.

    No matter the outcome, IFTLE hopes these business issues do not impact the outstanding work Elpida is doing in 3D IC.

    Next week we will finish updates from SEMICON Taiwan.

    For all the latest on 3D IC and advanced packaging stay linked to IFTLE..........

    IFTLE 68 2011 Semicon Taiwan SiP Global Summit Part 2. 3DIC Technology and Test

    September 24, 2011 9:47 AM by Garrou
    The SiP global summit was held recently in Taipai. Last week we looked at the some of the 3D technology forum. This week we will finish up on 3D technology and look at highlights of the 3D Test forum "Test Challenges and Solution in the New Era of Heterogeneous Integration," chaired by Mike Liang, president and CEO of KYEC. Multiple Packaging and Testing challenges must be met to meet the production yields required to take 3D from concept to commercialization. It is crucial that the entire supply chain of material suppliers, design houses, test equipment suppliers, and package and testing houses partner to develop cost-effective test mythologies and strategies.

    Victor Peng, SVP at Xilinx, updated the audience on their ongoing commercialization of Xilinx 7V2000T FPGA with their "stacked silicon interconnect technology" (SSIT).The company's FPGA 28nm slices are assembled "side by side" on a silicon interposer with 65nm interconnect wiring. They found the interposer was an excellent way to handle the 28nm chip low-k fragility.Chip fabrication, interposer fabrication and bumping is being done by TSMC. Chip bumping and module assembly is being done by Amkor.

    Peng reports that Xilinx is on schedule for sampling in calendar year 2011. Peng also noted that the company "believes in full 3D IC stacking (no interposer)" but that it will take a little longer for that technology to become standardized in the infrastructure.

    Recall in IFTLE 62 I discussed the nomenclature confusion part of which was "stereoscopic 3D" being confused with 3D IC. [ see IFTLE 62, "3D and interposers: Nomenclature confusion"] Well, I never thought I would see a presentation about 3D IC being used for stereoscopic 3D but that's just what happened when Taiji Utaka, SVP of technology platforms at Sony discussed the incorporation of 3D IC chips into the stereoscopic 3D Sony PlayStation. Sony is looking at the potential of improving 3D image quality by using 3D IC memory to increase performance (pixel fill rate improved by higher bandwidth) and improve latency. Sony sees the major impediment to using 3D IC as current cost, but also includes test protocol, thermal performance, proven reliability, standardization, and the availability of multiple suppliers as issues that need to be improved. Utaka interestingly noted that "game machines are required to have longer lifetime than PCs."

    Jim Walker, VP of semiconductor Manufacturing for Gartner during his presentation "Going Vertical" looked at "register DIMM" used in servers comparing the newly announced Samsung 32Gb DDR3 DIMM with through-silicon vias (TSV) to previous 32Gb RDIMM. He finds the TSV-based products operate at lower power and higher speed:

    -- Lower power: 4.5 Watts = 30% less than current 32Gb RDIMM without TSV
    -- Higher Speed: 1333 Mbit/sec vs. 800 Mbit/sec previous 32Gb RDIMM

    Eric Beyne of IMEC sees the current market divided into the following segments:

    Mobile consumer applications

    Memory/logic stacks:
    - Increased memory bandwidth, low power
    - Analog-logic stacks: Heterogeneous technology choices

    High-performance applications:
    - Very high memory bandwidth requirement
    - Very high power processor devices
        3D SI interposer substrates

    High density memory stacks:
    - High bandwidth, low power DRAM

    Microsystem integration:
    - Combining advanced logic and memory technologies with heterogeneous device technologies such as analog, sensor, actuator, MEMS

    Beyne concludes that it is difficult for designers to actually use the technology due to too many unknowns, and lack of 3D-EDA. The numerous technology options create a complex supply chain and make it difficult for equipment, material and EDA tool suppliers to develop the appropriate solutions. Thus, Beyne indicates that standardization is needed immediately in: 3D technology, 3D test, and 3D design.

    Roger Hwang, director of test at ASE, noted that test must be built into the 3D TSV assembly flow at the OSAT.

    At ASE, logic die will be tested after being mounted onto the substrate "strip" before singulation, and memory will be tested after tape and reel. Another test will be done to the final package after chip-to-chip bonding.

    Interposer test will be done after backside processing and after film frame mounting.

    Greg Smith of Teradyne listed the following unique TSV fault types:

    Faults can occur in the TSV itself:
    • Voids (High resistance)
    • Oxide pinholes (short to substrate)

    Faults can occur from bonding:
    • Contamination of bond surface
    • Misalignment
    • Height variation
    • TSV shorts

    Faults can occur from wafer thinning:

    • I-V degradation
    • Shifts in device performance

    For all the latest in 3D IC and advanced packaging stay linked to IFTLE.........

    IFTLE 67 2011 Semicon Taiwan SiP Global Summit: 3D Technology part 1

    September 19, 2011 9:19 AM by Garrou
    The SiP global summit was held recently at 2011 Semicon Taiwan in Taipai. It consisted of the 3D IC Test Forum "Test Challenges and Solution in the New Era of Heterogeneous Integration" chaired by Mike Liang, President and CEO, KYEC; the 3D IC Technology Forum, "Embracing the Era of 2.5D & 3D ICs" chaired by Dr. Ho-Ming Tong, GM and chief R&D officer, ASE Group; and the Embedded Substrate forum, "Bridging the Last Mile of Heterogeneous Integration" chaired by Dr. Kuo-Ning Chiang, Professor, director, Advanced Packaging Research Center, NTHU.

    Chairman Tong stood by the prediction he made at last year's meeting that serious commercialization of 2.5D and 3D ICs would likely begin in 2013.

    Takayuki Watanabe, VP of Elpida's TSV packaging development group, gave a detailed presentation entitled "TSV Technology for 3D DRAM." He described TSV production flow in Elpida where DRAM production and thinning is done in Hiroshima and stacking and assembly in Akita-Elpida.

    Their memory stacking process flow is shown below:

    In July Elpida announced sampling of their 8Gb DDR3 SDRAM [see "Elpida begins sampling 8Gb DDR3 SDRAM"]. The device is a "low power 8Gb DDR3 SDRAM that consists of four 2Gb DDR3 SDRAMs fitted to a single interface chip using TSV." Elpida believes that the new devices in notebook PCs will demonstrate a 20% reduction in operating power and a 50% reduction in standby power compared with systems that use the standard SO-DIMM configuration. Power consumption is reduced because the TSVs shorten the interconnect between the chips, thus reducing parasitic resistance and capacitance. In addition, chip height is decreased and the DIMM socket is eliminated. Chip mounting area is reportedly reduced 70%.

    A 16Gb module (consisting of two 4 chip stacks) occupies far less room (11mm × 15mm) than its SODIMM equivalent (67mm × 30mm) Details of the power savings comparison are shown below.

    Wide IO memory technology appears to be the future for mobile products mainly because it brings lower power consumption in a smaller, thinner package while being scalable for future bandwidth requirements. JEDEC is currently working to develop standards for such wide IO memory products.

    About a year ago Elpida Memory, Powertech Technology (PTI), and United Microelectronics Corporation (UMC), announced a 3-way 3D IC partnership to Elpida had previously announced their partnership with Powertech Technology Inc. and UMC to build 3D chips for the mobile, high-end graphics and computer markets. [see IFTLE 8, "3D Infrastructure Announcements and Rumors"]

    In terms of supply chain, Elpida/UMC/PTI propose the following:

    In a separate presentation, Scott Jewler, chief engineering, sales & marketing officer for Powertech Technology, showed their prototype line and the state of construction of their high-volume manufacturing facility.

    More info from Semicon Taiwan is coming soon. For all the latest in 3D IC and advanced packaging stay linked to IFTLE............................

    IFTLE 66 3M / IBM Seek to Improve Thermal Underfills; TSMC in Back End Packaging, Again

    September 10, 2011 1:11 PM by Garrou
    New thermal underfills for 3D chip stacking

    Earlier this week 3M and IBM announced that the two companies "plan to jointly develop the first adhesives that can be used to package semiconductors into densely stacked silicon "towers" [...] which will make it possible to build [...] commercial microprocessors composed of layers of up to 100 separate chips." While giving little technical detail, they announced that this proposed program could "potentially leapfrog today’s current attempts at stacking chips vertically" and offer low power solutions for "makers of tablets and smart phones". IBM was quoted as saying that IBM scientists are "aiming to develop materials that will allow us to package tremendous amounts of computing power into a new form factor -- a silicon "skyscraper." The picture that came along with the press release is shown below. It certainly makes it look like the chips are actually being simply glued together, but if this is 3D stacking with TSV then this would be a chips-last solution, and certainly that cannot be done with more than two layers at a time. My assumption was that this was an oversimplification for the non-technical press release.

    With the help of 3M and IBM I have made contact with Herve Gindre, division vice president at 3M Electronics Markets Materials Division, and Bernie Meyerson VP of research at IBM, to clarify exactly what is being proposed.

    3M’s Gindre indicates that indeed what we are talking about is basically a thermally-enhanced underfill, which he says "will help conduct heat through 3D multichip stacks and/or away from heat-sensitive components circuits." 3M will staff the program in the semiconductor division of its Electronic Market Materials business, which currently provides temporary bonding solutions and CMP consumables to the 3D market place. Gindre points out that 3M will be focusing their "years of commercial experience in composites, nanotechnology, adhesives and thermal interface materials" on the current problem.

    IBM will be running the program out of its semiconductor business unit. VP Meyerson declined to share much detail on timing or technology, which is to be expected since the program hasn’t even started. In terms of thermal performance specifications Meyerson offered that "we clearly wish to exceed current thermally conductive adhesive specifications to the point where the newly developed adhesive solutions at worst match those of silicon."

    IFTLE will be following any further developments in this interesting program.

    TSMC continues to scope out high-end IC packaging opportunities

    Digitimes reports that TSMC has undertaken in-house high-end packaging of ICs, produced by its foundry processes, for fabless IC design houses in the US and Europe [link]. This would obviously create competition for Amkor, ASE, SPIL, STATs and other subcontractors.

    At the last several TSMC spring Technology Symposia, in Silicon Valley, TSMC announced plans to expand its efforts in IC packaging. [see PFTLE 30, "Foundry TSV are comin’ -- TSMC makes their play for a biggerportion of the pie"] They have been doing wafer bumping, wafer sort, and wafer-level chip-scale packaging on a limited scale for years. At present, the company has two wafer bumping facilities, located in Hsinchu and Tainan. They are expanding their bumping and wafer-level chip-scale packaging technology and have announced copper pillar bump technology on 100μ bump pitch and will be manufacturing silicon interposers with TSV for 3D stacking. TSMC has announced that it is developing the interposers for Xilinx next-generation FPGAs and is in fact bumping them in-house rather than having that done at one of Taiwan's OSATS [see IFTLE 23, Xilinx 28nm Multidie PPGA?" and IFTLE 43, "IMAPS Device Pkging Highights: 3D IC"].

    According to that Digitimes report, "fabless IC design houses are willing to have TSMC responsible for front-end foundry and back-end packaging services although TSMC's packaging ASPs are higher than those of IC packaging/testing service providers." They conclude that this is because these fabless IC design houses like the convenience of a one-stop solution and worry about lower yield rates due to outsourced packaging. However, their sources add that "interestingly, so far, no Taiwan-based IC design houses have accepted TSMC's higher quotes for packaging services."

    Indications are that TSMC can generate gross margins of 50-60% for foundry services but even with their higher prices only 20-30% for packaging services. Thus some are questioning why they would expend precious equipment capex on the packaging side.

    Whatever your take is on this new information, it is clear that TSMC is slowly but surely moving into what was before a clearly defined packaging and assembly space.

    Update on Lester Lightbulb and the LED space

    Several of you have tried to leave comments on IFTLE 63, "Bidding Adieu to Lester Lightbulb" and one of you was actually peeved enough that you couldn’t, that you contacted our editor Jim Montgomery. Thanks for that, because it exposed a flaw in the new software that appears to be blocking comments. Jim says they are working on it. One issue appears to be my reported price for the EnduraLED 60W equivalent. One reader claims he has found them for $39 and even $19. Jim got interested in this and tells me that he can now find them for both prices in different parts of the country. All I can tell you is that the Home Depot price on the day the blog was written was $47. The one that I now have installed actually cost me $49.99 since I bought it locally (and still have the receipt). Anyway, my point is not that the price would never come down, but rather how far down it had to come to make purchase of this device a good business decision vs the CFLs. Both bulbs are still glowing brightly -- as well they should, well past my lifetime expectancy if I am to take their marketing propaganda seriously.

    Two other readers sent me email indicating that my concern over the life expectancy of the components in the bulb were well-placed, and that this certainly was not taken into account by Philips in their lifetime claims. I guess only Philips can answer that question.

    For all the latest on 3D IC and advanced packaging stay linked to IFTLE??????????????..

    IFTLE 65 Samsung’s 32GB RDIMM DDR3, GLOBALFOUNDRIES Packaging Alliance, Ziptronix Licensing News

    September 3, 2011 2:24 PM by Garrou
    Samsung Develops 30nm-class 32GB DDR3 for Next-generation Servers, Using TSV Technology

    In December of 2010 IFTLE announced “the Era of 3D IC had arrived“ following the commercial announcement by Samsung that is was beginning the mass production of 8 GB DDR3 memory modules based on the SODIMM form factor [ see IFTLE 27, “The Era of 3D IC has Arrived with Samsung Commercial Announcement”].

    Samsung has just announced the development of 32 GB DDR3 memory module (RDIMMs) using their 3D TSV packaging technology and their advanced 30 nm 4 Gb DDR3 chips. The modules can transmit at speeds of up to 1,333 Mbps, a 70 percent gain over preceding quad-rank 32GB RDIMMs (operational speeds of 800Mbps). Further, the 32GB-module consumes 4.5 watts of power per hour, reportedly the lowest power consumption level among memory modules in use in enterprise servers.
    Samsung has issued engineering samples of its new modules and is currently collaborating with CPU and controller designers to expand support for 3D TSV server modules.

    GLOBALFOUNDRIES and Amkor enter Alliance for Advanced Assembly and Test Solutions
    GLOBALFOUNDRIES and Amkor have announced that they have entered into a strategic partnership to develop packaging solutions for advanced silicon nodes. Amkor is thus the founding member of GLOBALFOUNDRIES’ new “Global Alliance for Advanced Assembly Solutions”. GlobalFoundries indicates that they expect to strike similar deals with other companies to create a broader alliance of packaging partners.
    As we have detailed many times in IFTLE, the move to advanced technology nodes has caused  packaging and interconnect solutions to become increasingly important. Packaging techniques are leading to improvements in performance and power-efficiency as well as reduced costs. IFTLE readers know that the adoption of 3D IC stacking of ICs is increasingly being viewed as an alternative to traditional technology node scaling at the transistor level. It is also clear that the ability to deliver end-to-end solutions such as 3D IC for customers will require such partnerships between foundries and OSATS to better enable supply chain management.

    At their recent “Global Technology Conference” [link] Gregg Bartlett, Sr VP of technology and research and development at GLOBALFOUNDRIES noted that “..the market is beginning to crystallize around certain subsets where system designers want to have that [3D IC]capability in hand,  he continues that “?customers will be demanding 3-D chip stacks late in the 28-nm node or early in the 20-nm node? big graphics and networking chips will demand 3-D chip stacks using interposers?mobile apps processors will want 3-D stacks using through silicon vias”. But, he warned, "?the [3-D IC] supply chain is nearly as complex as the technical solutions".[link]
    Indeed previous Globalfoundries roadmaps have shown 3D becoming “enabling” post the 32 nm generation.

    Ziptronix signs licensing agreement with Sony
    Ziptronix, Inc. has announced a licensing agreement with Sony Corporation for the use of Ziptronix’s patents regarding oxide bonding technology for backside illumination imaging sensors.
    Ziptronix has been touting their Zibond? oxide bonding technology for use in backside illumination (BSI) of CMOS image sensors for several years [ see  PFTLE 40, “Backside Illumination (BSI) Architecture next for NextGeneration CMOS Image Sensors]

     A back-illuminated structure minimizes the degradation of sensitivity to optical angle response, while also increasing the amount of light that enters each pixel due to the lack of obstacles such as metal wiring and transistors that have been moved to the reverse of the silicon substrate. Most of the CIS manufacturers have already moved to BIS technology per a recent market study by Yole
    Developpment [ see "CMOS Image Sensors Technologies and MArkets - 2010". CMOS BSI sensors BSI sensor technology is being used by Sony and has been announced in video camcorders and digital still camera products by Casio, Nikon, Ricoh, Samsung, JVC and Fujifilm among others. Ziptronix CTO Paul Enquist asserts that their patented ZiBond? technology, “?enables the industry’s lowest distortion for imaging systems utilizing backside illumination because of the oxide-oxide bond, alternate solutions, such as adhesives, fail to meet the industry need for ultra low distortion.


    In December 2010 Ziptronix filed a complaint against TSMC and Omnivision in Federal Court alleging infringement of several Ziptronix low temperature oxide bonding patents [see IFTLE 31, " Oxide Bonding Patent Litigation Has Begun"] .
     With Sony taking a license on the Zibond technology can Samsung, Toshiba, Cannon, Panasonic, Aptina, ST Micro or others who practice BSI  be far behind ?
    Ziptronix CEO Dan Donabedian predicts “? todays digital cell phone cameras that feature up to 5
    Megapixel cameras can advance to 16 megapixels using Ziptronix’s patented technology” and similar impact will be seen in “?digital still cameras, digital video cameras, automotive sensors and projection systems such as pico projectors”.  Chris Sanders, Dir. of Business Development notes that Ziptronx is currently “?actively engaged with multiple companies across the globe for licensing our technology in the bsi image sensor space” 

    For all the latest on 3D IC and advanced packaging stay linked to Insights from the Leading Edge???

    IFTLE 64 Semicon 2011 TechXSpots on “beyond 40 nm” and “3D deep sub micron”

    August 27, 2011 10:51 AM by Garrou
    The TechXSpot “Challenges and Solutions for 40nm and Beyond” was put together by Rich Rice of ASE and Tom Gregorich of Media Tek. Jim Walker of Gartner took a look at the macro trends effecting our industry including packaging.  Walker proposes the following :

    - between the 45nm and 8nm nodes, logic fab costs will double to $10 billion.
    - only four companies will be able to follow Moore’s law by 2018
    - the annual number of new fabs built will fall by 60% between 2011 and 2015
    - by 2015 foundries will account for ~ 1/3 of the value of all semiconductors compared with ~ ¼ today
    - by 2012, over 50% of packaging/test (SATS) will be outsourced
    - by 2015 more than $30 billion in annual R and D expense will be saved by collaborative R and D.

    Gartners estimation of total capacity availability by node and year is shown below followed by the fact that the finer feature chips are the ones driving packaging advances. Walker pointed out that between 1980 and 2010 the number of different packages available on the market has increased from 30 to more than 2200 !

    The TechXSpot session 3D in the deep submicron era was led by Jie Xue, Cisco Systems and Gamal Rafai-Ahmed, AMD .

    Eric Beyne of IMEC addressed the integration challenges for 3D-TSV with advanced devices.
    Beyne pointed out that the M1 metal layers “above” the TSV consist of very narrow, high aspect ratio lines which require very flat surfaces: low dishing of Cu TSV CMP. The ULK dielectric layers in lower metal layers are of reduced strength which requires stable mechanical properties in the TSV i..e quire optimized post-plating annealing conditions to avoid copper protrusion.

    Semiconductor devices are very strain-sensitive. Strain is actively used to increase the mobility in the nMOS and pMOS FET channels. The stress induced by the Cu-TSVs may cause variability among devices. The use of higher stress in the device channels reduces the impact of small variations due to TSV’s.  The strain in the Si substrates will impact planar devices differently than FINFET devices which are somewhat “decoupled from the substrate”.
    To reduce the impact of TSV stress on devices, a keep-outzone is defined around the TSV structure. For advanced nodes, reducing this KOZ to a minimum becomes more important.  The maximum stress induced in the Si by the TSV is in first order independent of the TSV diameter.  The stress levels in the Si are proportional to (ØTSV/r)2 , with r the distance to TSV center, thus scaling down the diameter of the TSV by x reduces the “effective TSV area” (TSV+KOZ) by x4 ! [As we have noted mnany times in IFTLE, the smaller the TSV (diameter and AR), the better]

    Jon Greenwood of GlobalFoundries addressed backside integration and supply chain challenges.
    When comparing 2.5 vs 3D integration Greenwood pointed out the following:
    2.5D Integration
    - For high performance applications, interposer option provides a thermal solution for near memory integration
    - TSV technology is required to enable Si interposer
    - Enables early TSV adoption
    - Bridges design readiness, TSV impact and CPI concerns on device
    - Typical interposer at 100 um thick allows time for back side and thin wafer handling processes to mature (increased system level yield)
    3D Integration
    - TSV middle technology is integrated into foundry process flows and node development
    - Quickly becoming low power and mobile centric due to thermal management concerns
    - Small form factor, high bandwidth applications
    - TSV design and layout is critical to device performance and reliability
    - Final device thickness typically at 50 um
    - Additional yield concerns associated with thin wafer handling
    They offer the following as what they view is becoming the standard TSV and backside processing flow.

    In terms of supply chain they envision the foundry plus vs the OSAT plus vs the third party models as shown below where the manufacturing solution, reliability and warranty ownership is in the hands of the foundry, the OSAT or the 3rd party respectively. Its probably pertinent to insert at this point that the Xilinx program choose to have TSMC manufacture and FC the interposer and thus chose option #1.

    Finally GF points out that while the substrate industry is stable and reliable, interposer delivery is a complete unknown.

    GF concludes with the following thoughts:
     - An integrated supply chain that offers customers yield accountability and competitive pricing needs to emerge
    - Interposer model needs to follow the organic BGA supply chain progression from the early
    1990’s to today
    - Japan Centric growing to Worldwide Supply Chain with multiple HVM suppliers located
    throughout Asia
    -Significant cost reduction and competitive pricing evolution –i.e.  over 90% cost reduction vs
    today’s pricingspan>
    - Substantial advancements in technology such as thickness reduction and warpage control, laser
    vias, build up technology.
    Ron Huemoeller of Amkor offered the following roadmap for silicon interposer products. While Amkor sees many TSV based products requiring an interposer, they see a severely constrained supply chain which is negatively impacting product proliferation.

    For all the latest on 3D integration and advanced packaging stay linked to IFTLE????????.




    IFTLE 63 Bidding Adieu to Lester Lightbulb

    August 21, 2011 4:03 PM by Garrou
    During the decade that my boys were growing up in Massachusetts, Massachusetts Electric had a great commercial on TV called “Lester Lightbulb” . Basically an incandescent light bulb with a smiley cartoon face on it told kids to remember to shut off the light when not in use and to not to put things into the electrical sockets. Energy savings is a good thing no matter what your politics are. Well I’m sure that most of you have heard that the US congress has convicted Lester of “wasting energy” and Lester is set to be executed next year unless someone can get him a clemency deal.

    I decided to take a look at the case against Lester and while doing so look at the packaging that reportedly is being used for his preferred high tech replacement ?the LED.
    Everyone knows the acronym KISS – or keep it simple stupid. Certainly Lester the lightbulb which has been around for more than 100 years obeys that law. I guess thats why mass produced light bulbs cost < $0.50 each.

    The US Energy Independence and Security Act of 2007 mandates new power consumption levels
    for general service lamps by lamp wattage starting in 2012. Current  100W, 75W, 60W, and 40W incandescent products will be required to consume no more than 72W, 53W, 43W, and 29W, respectively. The DOE very carefully states that the “EISA does not ban incandescent lamps; it increases the minimum efficacy levels” but it is very clear that there will be no imports and no manufacturing of bulbs that do not meet these requirements [link].

    There are an estimated 5B bulbs in use today. Anyone  wondering why the LED folks are going after the lighting market ?
    Compact fluorescents have been fully commercial now for several years and also use significantly less power than our friend Lester. Like their tubular precursors, CFLs contain a small amount (typically five mg ) of mercury. Mercury is toxic and especially harmful to the brains of both fetuses and children. Its use in applications from thermometers to automotive and thermostat switches have been banned. When a bulb breaks the mercury can be inhaled from the air or can settle into the carpet for future slow release toxicity. In many locations it is already illegal to throw fluorescents out with regular garbage, however recent  recycling data ( Association of Lighting and Mercury Recyclers) estimates a residential mercury bulb recycling rate of a mere 2 percent. The current energy star (EPA rating) average lifetime for CFLs is listed as 8000 hrs. [link]
    Popping open a CFL reveals a small PCB with ~ 20 components (mainly passives) loaded on its top surface. A bit more complicated than our old friend Lester.

    The U.S. Department of Energy has had a competition running to find a viable replacement for the  60-watt incandescent . It was just announced that after 18 months of testing the Philips Lighting North America bulb had won the DOE’s $10MM prize. The bulbs had to meet or exceed these requirements: “greater than 900 lumens at 10W or less for an efficacy of greater than 90W/lm at a color-corrected temperature of 2700-3000K and a color rendering index of at least 90”. The Philips bulb reportedly exceeded all these requirements during the 18 month trial. Original requirements called for a target retail price of $22 for the first year, $15 for the second year, and $8 in the third year they were offered for sale. Philips has said it plans to offer the bulb for retail sale as soon as early 2012 although reports are that it will sell for ~$60 due to the higher cost of its materials content.

    Philips already sells a 60-watt equivalent, the “EnduraLED” , at stores like The Home Depot,  although the prize winner is reportedly even more efficient. The prize bulb uses just 9.7 watts to match the light output of a 60-watt incandescent, compared with 12.5 watts for the product currently sold. The new lamp is also brighter than the one marketed now, at 910 lumens versus 800 lumens and reportedly  closer in color to a standard incandescent. The current EnduraLED (60-watt equivalent) currently sells for $47. The Warranty is 6 years, and Philips rates it at 25,000 hours of operation “it should last for decades if you take good care of it”. We’ll look more at the lifetime later in this blog.

    I am pleased to report to you that the CEO of Philips Lighting North America, reports that “...the origins and development of this product, as well as its future manufacturing are all in the United States?. In addition, we have publicly said we will use the L Prize money to expand the manufacturing of this product in the United States. We will do this internally [at Philips facilities] as well as with American partners”[link]. To which I say BRAVO?..seriously BRAVO !.
    In terms of  lifetime tests, “?.200 bulbs were installed in a lumen maintenance test apparatus in which ambient temperature was maintained at 45°C to simulate the elevated temperatures common in enclosed lighting fixtures. The bulbs were operated continuously. Spectral measurements were taken on each bulb every 100 hrs for the first 3K hrs and every 168 hours (weekly) thereafter. Data for the first 7,000 hours of operation were used to predict lumen output of the bulbs at 25,000 hours. Lumen maintenance is predicted to be 99.3% at 25,000 hours, significantly exceeding the 70% L Prize requirement [link].
    I personally would have an on off cycle where the bulb was switched off and then back on every 3 hours to mimic the daily use because we all know that bulbs usually burn out in the power on cycle, not while they are lit (at least that’s true for incandescants). This also only indicates to me what the projected light output would be at 25K hrs, not that the bulb will be functional after 25K hrs. More on that later.
    I looked for a teardown of one of these bulbs to see how they were packaged and found one [link]

    (A) The yellow plastic is the phosphor coating on the cover. Because it is located separately from the LEDs its called a remote phosphor. Popping off the phosphor coated covers we see the LEDs mounted vertically on the interior central column on the bulb. The LEDs are mounted on a little PC board which is a bit more complex than the CFL board (tongue in cheek) . The large amounts of metal (this is one heavy bulb) are used as the heat sink to conduct the heat away from the LEDs.
    I decided to do just a little math to see if I could justify all the enthusiasm being generated for this bulb (after all the advertising on the Philips LED package says I’ll save me $147 over the life of the bulb !)
    Below shows what I was able to find selling at my local Home Depot (An American hardware store).

    The DOE tells me that “60W-equivalent LED A-lamps (the one listed in our table) at $40 per bulb is 6.3 years at average electricity rates.

    The government officials like to point you to the “hypothetical” curve of the $5 LED bulb which pays off in 0.8 years , but?well if Lester had a voice he’d say that if a Mercedes cost $10,000 he would buy one of those instead of a Ford fusion?.know what I mean.
    My local Duke Power rate is 0.08/kWH and both I and the Govt agree that a light bulb is probably on for about 3 hrs a day. So the incandescent that lasts for 1000 hrs gives me 333 days of use or 0.91yrs and costs me : 3hrs x $0.08 /KWH x 0.06KWH/hr = 1.4 cents per day or $5.25/yr  or a bulb + power cost of $6.17 / yr . Using the same calculations CFLs would run $2.40 / yr and the LED would cost $2.16/yr.
    Lets look at the Philips claim of $142 savings. Going out to 25,000 hrs (at 3 hrs/day thats 22.8 years ! - Hard to know what energy will cost 2 years from now let alone 23 years from now, but at todays prices the total cost for 23 years for the LED bulb is $49.68 vs our friend Lester at $141.9 for a net savings of $92 or a savings of $4.00 per year per bulb ( Philips must be counting on the price of power going up in their calculations).

    (1) The CFL and LED technologies, while they will certainly use less energy, are much more complex and simple volume scaling will not take them to the cost of an incandescent bulb.
    (2) Are all the components on the PCBs really rated for 7.3 let alone 23 years use ? That’s longer than the ATandT telecom standards ! I am not convinced that anyone has determined whether all the passive components currently used on these devices will last that long and if they don’t, it will not matter if the bulb was outputting 800 lumens at the time that the bulb failed. As we all know, a device is only as good as its weakest component.
    (3) Savings are tied to two main variables: (a) cost of power and (b) lifetime of weakest component. Increased price of energy makes them look better and failure of any of the components in the bulb will make their relative price increase significantly. For instance if a capacitor fails on the LED bulb after 4 years the new cost would be $12.80 / yr or double the cost of an incandescent. In fact the LED bulb needs to last 9 years to be equal to the cost of the incandescent.
    (4) Since the CFLs will cost more than 7X less than the LEDs most families, when faced with changing > 20 bulbs per household in the period of a year, will move to CFLs. Changing 4B bulbs to CFLs in a year will increase the mercury released to the environment by ~ 20,000 Kg with much of this concentrated in the urban areas where our population is concentrated.
    (5) IFTLE predicts that theft of light bulbs from public places will increase significantly in the future !
    IFTLE has purchased said CFL and LED bulbs and they became operational on 8/15/2011. I will report back to you periodically on our real life testing. The breakeven point will be 8/15/2020 ??.. anyone taking bets ?
    For all the latest on 3D IC integration and advanced packaging stay linked to IFTLE?????

    IFTLE 62 3D and Interposers – Nomenclature confusion; Equipment Market Shift to Pkging Continues

    August 15, 2011 9:30 AM by Garrou
    Some of you might remember a  late 1970s comic routine called “Raymond J. Johnson Jr” The character (shown at left) becomes annoyed when addressed as "Mr. Johnson" and exclaims  "My name is Raymond J. Johnson, Jr?.now you can call me Ray, or you can call me J, or you can call me Johnny, or you can call me Sonny, or you can call me Junior; or you can call me Ray J, or you can call me RJ, or you can call me RJJ, or you can call me RJJ Jr but you don't hasta call me Mr. Johnson!"

    Lots of equivalent names for the same person. Sometimes that happens in science and sometimes the exact opposite happens where lots of different things are all known by the same name – for instance 3D.

    3D Confusion
    At the recent Suss Workshop at Semicon West, I started of my 3D IC status lecture by pointing out the confusion occurring in the trade press about the term “3D”. Below is a copy of the slide that I used . The culmination for me was the report released by the Taiwan trade development council July 5th with the catchy headline “TSMC may beat Intel to 3D chips” With a title like that this piece was widely picked up by the trade press and reprinted dozens of times on blogs and web pages by that evening. The example that I gave on the slide is EE Times (because it is the most prestigious of the lot) who appropriately referenced the original source (which may I say many others did not do) . In this haste to get material out to “the readership” no one appeared to have read the article to see that the original report was comparing apples to oranges or in this case TSMC 3D IC with TSV to Intels announced finFET 3D IC transistor structures [ see IFTLE 50 “Words of Wisdom”] . I’m sure the trade development council authors, simply didn’t know the technical difference but the “copy cats”, those who cut/paste and reprinted ?.well they either also lacked the technical acumen to know the difference or simply didn’t read it. EE Times corrected the story on July 11, curiously the same day the blog “SemiAccurate” lambasted them for their reporting [link]
    When it comes to 3D be careful that you understand what your reading about and don’t always trust that the author has the knowledge or took the time to do the same. 

    Silicon Interposers , 2.5 D or Silicon BGA
    Looking back over the development of what is now commonly known as “silicon interposers” or “2.5D” as ASEs CTO Ho-Ming Tong has been calling them [see IFTLE 18, “The 3D IC Forum at 2010 Semicon Taiwan”] long time IFTLE (and PFTLE) readers are aware that I was not initially enamoured by silicon interposers due to my past experiences in “MCM-D” technology and was calling them silicon BGAs for awhile.[ see PFTLE 79, “Experience or Prejudice? Si Interposers Using TSV”] My views moderated with time as it became clear that there were strong drivers for Si interposers, this time around [ see PFTLE 109, “You Cannot Resist an Idea Whose Time has Come”]
    The other day I decided to google “silicon ball grid array” and come up with a patent issued to old friend Dave Palmer, recently of Sandia. To be exact we are talking USP 6,052,287 filed in Dec of 1997 and issued in April of 2000 which gives it another 6 years of life. If your in the business of making or using such interposers, you might want to give this patent a look !
    Others point to the IBM patent  3,343,256 (1964) “Methods of Making Through connections in Semiconductor Wafers” and contest the validity of the Sandia patent. Only a legal battle will truly tell !
    Cannon latest to enter packaging market.
    With the number of players decreasing with each succeeding generation of scaling [ see PFTLE 121 “IC Consolidation, Node Scaling and 3D IC”] it is only logical that front end IC equipment vendors would be looking at the IC packaging market as an area into which they can expand.
    In  April 2009 , PFTLE openly proposed that Applied appeared to be positioning to become  a “one stop shop” for those interested in 3D IC (see PFTLE, “Samsung 3D ?Roadmap’ That Isn’t").  In June of 2010 I added Novellus to that list as they announced a series of products aimed at the wafer level packaging and 3D IC with TSV markets [ see IFTLE 3   “.....on Finding the Beef and Finally Addressing 3-D IC” ]

    The latest equipment supplier joining the group is Cannon who  made its first foray into the semiconductor back-end packaging equipment market with a lithography tool for through silicon via (TSV) and bumping.   Canon modified their  front-end tool series to accommodate the thicker resist films used by TSV and bump structures.  The system's projection lens optics expose 52 x 34 mm, compared with the 26 x 33 mm area exposed by front-end tools.

    For all the latest on 3D IC and advanced packaging stay linked to IFTLE??

    IFTLE 61 Suss 3D Workshop at Semicon West

    August 7, 2011 6:00 PM by Garrou
    This week, lets take a look at some of the presentations from the Suss MicroTech workshop “3D Integration – Are We There Yet” which was held at Semicon West in July.  

    Eric Beyne,  IMEC Scientific Director for 3D Technologies, addressed the technical issues of carrier systems for 3D TSV thinning and backside processing. Beyne points out that right now silicon carriers are favored over glass because the glass, while transparent which allows for laser based optical debonding techniques, must be CTE matched to silicon over a large temperature range; ground to tight TTV specification (high cost ?) and has a negative effect on plasma based post grinding backside processes due to its low thermal conductivity.
    After alignment and temporary bonding Beyne recommends the use of use of in-line metrology to allow for wafer rework if necessary.

    Rama Puligadda, Mgr. for Adv. Materials R&D for Brewer Science gave an update on their ZonebondTM  room temperature debonding process.  The Zonebond process basically uses a 2.5 mm ring of adhesive to hold the wafer in place for grinding and backside processing which allows for easier subsequent debonding. The thin wafers are released from the carrier at room temperature after mounting on a film frame. Blanket UV exposure on the flex frame allows solvent removal of the temporary adhesive without damaging the adhesion to the flex frame tape.

    Brewer has also developed a process with two carriers in order to achieve a wafer flip.


    Stephen Pateras, Product Marketing Dir. at Mentor Graphics, gave a presentation on advanced design for test (DFT) and built in self test (BIST) for 3D-IC structures.  Pateras points out that TSVs can be used to create test access paths so that all BIST resources can be accessed on any device.

    Pateras also concluded that all EDA players need to support common test access infrastructures since this will be required to stack die from difference sources. 
    Eric Strid, CTO of  Csacade Microtech, indicated that they are using MEMS techniques to produce lithographically printed probe cards capable of 6 µm sq. x 20 µm high probe tips on 40 µm pitch which are being sold in research quantities.

    Strid pointed out that standard pad locations will be required for vendor interchangeability and that standard materials specs for pads are needed in terms of materials, thickness and flatness. Such standard pad locations will enable standard test tooling.
    Stefan Lutter , Bonder Project Mgr for Suss, discussed equipment and processes for temporary de-bonding. Suss reports that their open platform approach is capable of using any of the following bond/debond technologies. They see the industry trend as moving to the newer room temperature (RT)  release processes.

    They claim that their HVM equipment, available 4Q 2011, will be capable of bonding and debonding 20-25 wafers/hr. The new Suss MicroTec product introduction is a HVM debonder/cleaner line for the RT release processes.
    Thinned wafer on carrier mounted to flex frame are fed to these modules and thinned wafer on flex frame and detached carrier are generated. The technology uses a porous vacuum chuck to hold the thin device wafer that is mounted on tape and a flexible plate with vacuum grooves and debond initiator to peel-off the carrier. A schematic of the cleaning process is shown below.

    For all the latest on 3D IC and advanced packaging stay linked to IFTLE






    IFTLE 60 Semicon 2011: ASE, Alchimer, SPTS

    July 29, 2011 9:52 AM by Garrou
    Wu of ASE discusses Semiconductor Industry Status

    At the recent Semicon West event in San Francisco, Tien Wu, COO of ASE, was the keynote speaker at the opening ceremony. Prior to joining ASE in 2000, Wu held several management positions within IBM.

    According to Wu, the 53 years old semiconductor industry now accounts for 0.6 percent of worldwide GDP. He sees the semiconductor growth rate converging to ~ 7%. For the period 2011-2015 he is forecasting four years of stability with “mild growth” He sees this as a period of consolidation where only bold companies (“the bold ones”) will continue significant R&D and CAPEX spending. Wu described growth in the semiconductor industry over the past several decades as being driven by key applications. Aerospace in the 1970s, mainframe computers in the 1980s, PCs in the 1990s (global penetration now ~ 20%) cell phones in the 2000s (global penetration ~ 60%) and smart appliances in he 2010s . Wu noted that all of the applications are still running in huge volumes today.

    Wu sees the industry polarizing into two factions ; (a) the infrastructure faction consisting of manufacturing heavyweights and (b) a systems faction [ IBM, HP, Apple] using software to interweave their product solutions and worrying about “branding “ their products. To quote Wu “The manufacturing heavyweights are driven by the systems power houses”

    When comparing front end and back end operations Wu quoted figures showing that from 1980 to today $500B in CAPEX has been spent on the front end operations (avg of $26B/yr) whereas only $133B has been spent on the back end.
    (ASE team joins COO Wu on stage after his Semicon Plenary lecture)

    Alchimer Electrografting for MEMS, 3D and 2.5D Interposers

    Steve Lerner, CEO of French startup Alchimer [see PFTLE 124; IFTLE 12] notes that progress is being made using their electro and chemi grafting products in the MEMS arena.  Earlier this year Alchimer  announced that the Microelectronics Innovation Collaborative Centre [C2MI (Quebec)]  had licensed Alchimer’s Wet Deposition process for MEMS 3D Research [link] to support the center’s 3D MEMS programs.
    Luc Ouellet, VP of R&D at Teledyne DALSA Semiconductor (an earlier Alchimer licensee) reports that Alchimer’s electrografting technology “??.provides strong support for work in advancing the technology for 3D MEMS manufacturing with a cost-effective approach”
    Lerner also indicates that their new product family “AquiVantage” which provides metallization
    for 3D Interposer and via last (backside) packaging is showing significant cost reduction for these applications.

    AquiVantage uses the same basic technologies as the Alchimer’s wet processes for TSVs, reportedly providing concurrent wet deposition of TSV and front-side isolation, barrier, and copper fill/RDL, while eliminating CMP and dry deposition steps. It also supports smaller vias with higher aspect ratios. On the backside, the AquiVantage process allows selective maskless growth of the on-silicon isolation layer, eliminating an expose/develop/etch/clean lithography process cycle.

    IFTLE sat down with Paul Linder, executive technology director and Markus Wimplinger director of EVGs business unit for technology development and intellectual property, to discuss their views on 3DIC commercialization and better understand their new temporary bonding metrology module which seeks to minimize the product at risk in a production environment.

    Wimplinger noted that they have 1 customer already in production and that several are very close. Although they are wary to name names without customer approval , we have all seen their joint announcements with Amkor and their equipment installed at the joint programs of Leti / ST Micro and Fraunhofer Dresden and Global Foundries.

    When asked to sum up their activity in the now retired EMC-3D consortium of which they were a co-founder, Linder indicated that the EMC-3D roadshows were helpful to show the industry that there is a supply chain for 3DIC and that the technology was doable. Linder reports that by the end, there was a clear consensus on a std process flow and all in all he views this as a very successful collaboration.

    EVG has recently announced that they have joined the Ga Tech 3D Systems Packaging Research Center as a Manufacturing Infrastructure Member. Linder indicates that their mission is to develop “?technologies that will make silicon and glass interposers with TSVs a truly affordable packaging solution." EVG's temporary bonding and debonding, chip-to-wafer bonding and lithography technology and process know-how will be included in the PRC's Silicon and Glass Interposer Industry Consortium research program.

    EVGs new inline metrology module reportedly allows customers to implement in line process control for thin wafer processing. The in line metrology module can detect a variety of process irregularities and defects during temporary bonding and debonding including the TTV (total thickness variation) of the carrier wafer, adhesive layer, bond stack and thinned wafer; bow/warp of the boded stack and voids in the bond interface.

    For all the latest in 3D IC and advanced packagign stay linked to IFTLE.....................

    IFTLE 59 Thin Film Polymer Apps from the 2011 ECTC; Tezzaron 3D Activity

    July 22, 2011 10:40 AM by Garrou
    Polymer filling technology for Vias last (backside) TSV

    Leti presented informative data on polymer filing of vias last (backside) TSV. The normal Leti process a wafer is bonded on a temporary glass carrier and thinned down to 120µm. 40-60µm diameter vias are then performed by DRIE in silicon. A 2µm thick SiON insulation layer is performed by PECVD. A plasma etching is then performed to open contacts on metal level in TSV bottom. Due to the TSV dimensions complete filling with a metal is not appropriate due to issues including process time, process cost, metal overburden thickness and thermo-mechanical stress. For these reasons, a copper liner is electroplated inside the TSV. This liner also forms the RDL layer on the wafer bottom surface. A 7µm thick polymer layer is then coated on the RDL in order to insulate it This layer, realized by spin-on of a liquid polymer, tents the RDL and TSV without filling it, as shown in the figure below. This leaves the copper liner inside the TSV exposed to trapped air (oxidation).  In addition, the thin polymer layer over the TSV is a weak point where temperature variation (during following process steps or device lifetime), can break or crack the layer.

    In the modified "polymer fill" process a 20 to 30µm thick polymer layer is coated by spin-on on the wafer. Vacuum heating is performed decreasing the polymer viscosity and  allowing easier removal of the air trapped in the TSV. Temperature and the pressure during the vacuum heating has to be optimized for each different polymer in order to obtain complete filling of the TSV.

    Trials have been done with two polymers having different thermomechanical properties (see table ).

    Polymer 1 has a higher Young modulus and a lower coefficient of thermal expansion than polymer 2. Results show that polymer 1 induces more warpage in the thinned wafer than polymer 2

    Fan Out WLP by RDL first Method
    Researchers at Renesas described a unique process flow for achieving fan out WLP (FOWLP) by an RDL first method.  The fabrication technology used for most FOWLPs is a chips first method (shown in the figure below) where the chips are mounted to a carrier face down; the chips are molded into a wafer and the carrier removed; RDL and terminations are formed and the packaged chips subsequently singulated.  Renesas repots limitations to this process flow include (1) The I/O pitch of the embedded chip is limited by alignment mismatching between the chip and the RDL; and (2) The RDL requires a low-cure temperature resin which may negatively affect package reliability.
    Renesas suggests a RDL first approach which they note is based on their earlier work with NEC on the SMAFTI program ( smart chip connection with feed through interposer). The process flows are compared below.

    They claim that a finer chip I/O pad-pitch is achieved due to better CTE  matching between the die and support wafer and that the high-cure-temperature resins used, make the RDLs more reliable. Their name for this is SiWLP for SiP (system in package) WLP. Another acronym I greatly dislike since it will always be interpreted as "silicon WLP" for obvious reasons.

    The figure below compares a WB-BGA solution to a SiWLP solution for a 6 mm2 analog chip and a 3 mm2 microcontroller. It indicates that the SiWLP enables a 57 % reduction in area compared to conventional WB-BGA-type SiP.

    Mechanical Properties of Thin Film Polymers
    A joint publication between RTI Int, U Texas-Austin and Microelectronic Consultants of NC took a close look at the mechanical properties of low temp ( ca 200 C) cure polymers [Asahi Glass-ALX; Hitachi-DuPont-PBO and JSR-WPR 5200]used in RDL type applications. Getting thin film specimens [10-20µm thick samples] properly fabricated and loaded into a test system is not a trivial task. Reproducible data requires samples that are lithiographically prepared (not cut with a razor blade) and requires compliance correction factors be calculated. The following table shows vendors reported data vs data gathered in this study. Manufacturer reported modulus numbers were in all cases off significantly (ca 50%) and in some cases elongation and tensile strength numbers showed quite a large spread indicating that even in this study, where extreme caution was taken to prepare the samples, flaws must have been present.

    PFTLE and IFTLE have previously covered Tezzaron, one of the pioneers in 3D IC [ see PFTLE 125, PFTLE 115, PFTLE 90; IFTLE 8, IFTLE 28]
    We recently revealed that MOSIS working with Tezzaron and Mentor Graphics would now allow users to test out 3D-IC concepts using the standard Tezzaron 3D process. [link]
    MOSIS is gathering participants and will manage the program.  Tezzaron CTO Bob Patti reports that they will "...provide the PDK (design kit), assist with 3D design issues, do the 3D assembly, and deliver the finished components".
    Patti also reports that their 3D IC customer program activity is increasing exponentially. Since customers have not identified themselves publicly, Tezzaron cannot say who they are.  They also aren't at liberty to describe the chips in any detail, however Patti indicates that the devices include:
     - More than one multi-core processor - Smart temperature sensor
    - Synthetic aperture radar processor - ADC based I/O receiver
    - Cellular automata FPGA system - Synchronization and power delivery architectures

    For all the latest on 3D IC and advanced packaging stay linked to IFTLE.....

    IFTLE 58 Fine Pitch Microjoints, Cu Pillar Bump-on-Lead, Xilinx Interposer Reliability

    July 18, 2011 9:57 AM by Garrou
    Just finished a trip to Semicon West and a short vacation in New Mexico with the kids I grew up with many years ago in "the city". For those with interest in NYC in the 50's and 60's try out our web page at

    Several of you at Semicon West requested that I make the figures larger (i.e more readable). I am stuck with the limitations of "blogger" software which is very HTML sensitive but I will try.

    Anyway, this week we will continue to take a look at packaging activities at the 2011 ECTC.

    IMC formation in fine pitch microbumps

    Samsung found that Ni3Sn4 IMC formations at interface between SnAg solder and their 4µm Ni UBM degrades the mechanical properties of solder joint, and increases resistance of solder bump. IMC growth rate and Ni UBM dissolution rate were calculated.

    Thin IMC changes into thick IMC during HTS. During 150°C annealing for 1300 hours, Ni UBM was converted into Ni3Sn4 IMC. Even though there are such microstructure changes, resistance of micro bumps were not changed during HTS 150°C. Resistance started to degrade after 1000 hours at 180°C due to void formation at interface between IMC and Al trace line. They found that open failure occurred when Ni UBM completely consumed and failure time is consistent with total consumption time of Ni UBM.

    ITRI reported similar results on their 12µm microbumps (5µm Cu/3µm Ni/2.5µm SnAg) on 20µm pitch. The intermetallic phase formed at the interface was identified as Ni3Sn4, the thickness of this layer increases with time and/or temperature in agreement with the results of Samsung. They also found problems with seed undercut during processing. When the thicknesses of the Cu seed layer sputtered on the wafer was reduced from 5000Å to 2000Å and a dry etching was used to remove the seed layer after bump plating and PR stripping, the undercut of Cu posts could be confined to less than 10%. A dramatically undercut Cu pillar (left) takes on the appearance of mushroom plating.

    ITRI reports that conventional reflow with flux is seldom used for the assembly of microbumps because the gap size between chip and interposer, i.e. 20µm, makes it difficult to remove flux residues which could cause void formation within the underfill and degrade the reliability.

    Copper pillar bump on lead

    Qualcomm and STATS ChipPAC reported on the unique combination of copper pillar bump and bump on lead (more accurately called bump on trace). Their suggested acronym CuBOL just doesn't identify the structure well enough for me, so I prefer and humbly suggest CPBOL for copper pillar bump on lead.

    The technology which utilizes the fcCuBE technology of STATS ChipPAC (see USP 7368817), involves using Cu pillar bump attached to a narrow trace or "bond-on-lead (BOL)" without any solder resist confinement (open SR) in the peripheral I/O region of the die. This enables improved routing efficiency on the substrate top layer thus allowing 4L to 2L reduction in the substrate without compromising functionality. The cost of the FC package is lowered by means of reduced substrate layer count, removal of solder on pad (SOP) and solder mask and relaxed design rules. BOL or narrow pad which takes significantly lower space on the top layer allowing more area for escape routing; thus enables relaxed Line / Space (L/S) design rules which in turn help to lower the substrate cost significantly. Similarly, the 'Open SR' concept in CuBOL further allows additional escape routing to be fit in the same bump-to-bump spacing; which offers increased routing efficiency and I/O density on the top most layer. The combination of BOL and Open SR together thus allows conversion of 4L substrate design into 2L without compromising I/O density.

    Fluxless chip-on-wafer (C2W) bonding

    ITRI reported on their studies fluxless joining of 30µm pitch Cu/Ni/Sn-Ag bumps. In this study, the Ar + H2 plasma treatment was applied on the C2W process for the purpose of tin oxide removing and enhancement of the bondability. During bonding they found that gap control was very important since poor control could lead to a narrow necked joint ( c) or solder ozzing out of the joint and possible causing shorts (b).

    After bonding and underfilling, temperature cycling test (TCT), high temperature storage (HTS) at 150°C, highly accelerated stress test (HAST) and electromigration (EM) reliability were performed on the chip stacking module to evaluate the reliability of solder micro bump interconnection assembled by the C2W process. Without underfilling a significant number of samples failed . With underfilling HTS greater than than 2000 hrs; TCT greater than 3000 cycles and HAST testing were confirmed.

    Reliability of Xilinx interposers

    Xilinx shared some of the reliability data on their 28nm FPGA with interposer structured. Recall the chips and the interposer are manufactured by TSMC, the interposer is bumped by TSMC, and the chips are bumped by Amkor. The final assembly is done by Amkor [see IFTLE 23, "Xilinx 28nm multidie FPGA..."]

    The silicon interposer test chip with thousands of micro-bumps at 45µm pitch has been fabricated.

    The silicon interposer is 100µm thick, and is mounted on a 42.5mm×42.5mm substrate through 180µm pitch C4 bumps. The TSVs are typically 10-20µm in diameter and 50-100µm deep. The walls of the TSV are lined with SiO2 dielectric. Then, a diffusion barrier and a copper seed layer are formed. The via hole is filled with copper through electrochemical deposition. The interposer wafer is thinned to expose the TSV from the bottom side. The Cu overburden is removed by CMP followed by passivation and UBM process. C4 bump is electroplated and reflow soldered on top of the UBM layer. FPGA wafers are bumped to ultra-fine pitch in the range of 30-60µm using Cu pillar bump technology. The FPGA dies are diced and attached to the interposer top pads. The gap between the interposer and the FPGA die is filled using underfill material to protect the micro-joints. X sections of the overall assembly, the interposer and the micro joints are shown below.

    Main focus of this study was to understand the impact of moisture and temperature cycling on the microbumps and adhesion of the underfill to top FPGA die and thin TSV interposer substrate. Underfillls were first evaluated and found to perform better with no clean flux. Plasma cleaning was implemented before underfilling and gap height was increased to improve underfill flow.

    With improved gap height and plasma cleaning, no delamination was observed either in L5 preconditioning or after 264 hrs of HAST at 110°C. All the samples passed 1000 cycles of TCB. Cross-sectioning of interposer after 1000 cycles confirmed that there was no protrusion of TSV. An example of cross-section of micro joint after 1000 TCB cycles.

    Fraunhoffer through mold vias

    Fraunhofer IZM examined chip embedding into polymer by molding and redistribution by PWB technologies for highly integrated low cost packages.

    The general process flow starts with the lamination of an adhesive film to a carrier. This adhesive film has one pressure adhesive side and one thermo-release side (heating the tape, the thermo-release side of the tape loses its adhesion strength). Dies are placed, active side down, towards the carrier. Molding is done by large area compression molding. For chip redistribution, resin coated copper is used. After lamination of the RCC film on both wafer sides in one step, micro vias are laser drilled to the die pads and through mold vias in the same process step to connect to and bottom side. By plating both, via filling and die pad connection to the copper layer and the top copper layer to the bottom copper layer are achieved.

    Mold materials with small filler particles (maximum filler particle size of 25µm) allow the fabrication of vias with a very precise and smooth via surface but materials with finer fillers currently have higher viscosities and lower filler content leading to a higher CTE.

    For all the latest in 3D IC and Advanced Packaging, stay linked to IFTLE...

    IFTLE 57 Elpida and MOSIS Ready for 3D IC ; TSV Going “Where the Sun Don’t Shine”

    July 9, 2011 9:41 AM by Garrou
    Elpida Announces Ultrathin PoP 3D Packaging

    In late June Elpida announced what it claims is the thinnest available DRAM device, a new 0.8 mm four-layer package of 2GB DDR2 mobile RAM chips, assembled using package-on-package (PoP) technology. [link]

    Customers have been using two-layer 0.8mm packages, rather than the thicker 1.0mm four-layer PoP, so systems needing 8GB of DRAM needed two stacks of 4GB product. Now they can get four layers of 2GB in one package. Yields and cost are reportedly the same as for existing 1.0mm products. Advantages of PoP for mobile devices includes: mounting space is reduced, individual packages can be tested, less wire bonding used (minimizes losses. Volume production ramp is slated for 3Q11.

    3D IC Memory Stacks with TSV Now Shipping

    A few days later Elpida, who exactly a year ago made headlines as the first to announce commercialization of memory stacked with TSV, [ see IFTLE 8, “3D Infrastructure Announcements and Rumors”] has now announced that it had begun sample shipments of DDR3 SDRAM (x32-bit I/O configuration) made using TSV stacking technology.[link]

    The device is a “low power 8-Gb DDR3 SDRAM that consists of four 2-Gb DDR3 SDRAMs fitted to a single interface chip using TSV”. Target applications reportedly include tablet PCs, extremely thin PCs and other mobile computing systems. The new TSV DRAM will reportedly enable significant energy savings as well as making portable electronic devices smaller, thinner and lighter. Elpida believes that the new devices in notebook PCs will demonstrate a 20% reduction in operating power and a 50% reduction in standby power compared with systems that use the standard SO-DIMM configuration which use standard wire bonding technology. Power consumption is reduced because the TVSs shorten the interconnect between the chips, thus reducing parasitic resistance and capacitance.  In addition, chip height is decreased and the DIMM socket is eliminated. Chip mounting area is reportedly reduced 70%.
    This latest Elpida announcement serves to back up the statement that global 3D roadmaps appear to be converging on 2012 as the breakout year for TSV based memory stacking. [see “3D roadmaps Begin to Converge”]
    MOSIS ready for 3D IC prototyping
     In mid June MOSIS announced their Multi Project Wafer (MPW) services would now allow users to test out 3D-IC concepts using the same provider and model they currently use for their standard semiconductor processing. MOSIS has previously been known for its  low-cost prototyping and small-volume production service for VLSI circuit development [].

    Working with  Tezzaron and Mentor Graphics, MOSIS will manage MPW projects including reticle creation, fab reservations, final packaging and testing, and other logistics.
    The Tezzaron process will enable designs using tens of millions of TSVs with dimensions as small as 1.2 x 6 um and 2.4 um pitch, producing up to 300,000 vertical interconnects per mm sq. Tezzaron will also provide backend manufacturing steps including wafer thinning, backside metal and wafer bonding.
    Mentor Graphics provides DRC and LVS tools that support 3D-IC physical verification, ensuring that designs are correct and will meet 3D process requirements and are manufacturable.
    Customers can use the MOSIS 3D-IC service to create proof-of-concept ICs that demonstrate the use of high-density TSVs in various applications.

    TSV Going Where the Sun Don’t Shine
    Medigus, a leading developer of endoscopic and visualization medical devices, and TowerJazz, announced successful sampling of the second generation of TowerJazz's CMOS imager that serves in Medigus' line of disposable miniature cameras. The use of disposable cameras eliminates the need for the very expensive and time consuming sterilization process commonly associated with endoscopic procedures. The camera’s diameter is only 0.99 mm, the first video camera in the world with a diameter smaller than 1 mm. Medigus will begin supplying samples of the camera to customers in Japan and in the US for cardiology procedures. The camera will be integrated in Medigus’ other endoscopy products.

    The disposable camera sensor will be manufactured in TowerJazz’s Fab 2 using its 0.18-micron CMOS image sensor process and will be integrated into the camera produced in Medigus' manufacturing facilities. TSV are used to minimize the camera’s size and reduces production costs in high volumes.

      For all the latest in 3D IC and Advanced Packaging stay linked to IFTLE?..

    IFTLE 56 Electromigration at the 2011 ECTC

    July 3, 2011 11:23 AM by Garrou
    [apologies for the formatting issues in IFTLE 55. With the move of SST to the "new platform" issues appeared when loading and editing IFTLE. Hopefully those issues are now resolved, and will never be seen again !]

    We continue with our look at the major themes presented at this years ECTC Conference. This week we will look at presentations concerning Electromigration (EM).

    Electromigration continues to be a topic of intense study. Several papers have reached the conclusion that copper pillar bumps are more EM resistant that normal UBM/ bump structures. Many groups are also concluding that the smaller micro bumps are also more resistant to EM.

    ASE has released data from their studies on the effect of EM on RDL traces in wafer-level whip-scale packages. The first RDL structure was sputtered Ti/Al/Ti (0.2um/1.5um/0.2um) combined with a sputtered UBM: Al/Ni(V)/Cu (0.4um /0.325um /0.8um). The second RDL structure consisted of Ti/Cu/Cu (0.1um /0.2um /4, 6, or 7.5um electroplated Cu) combined with Ti/Cu/Cu UBM (0.1um /0.2um /8um electroplated Cu).

    Based on Weibull characteristic lifetime plots derived from their data, ASE indicates that the maximum allowable electric currents for 100,000 h (11.4 years) continuous operation without electromigration damage for Ti/Al/Ti and Ti/Cu/Cu RDL with 25um wide RDL traces. The results indicate that Ti/Cu/Cu RDL performs better than Ti/Al/Ti RDL at low operating temperatures while features relatively shorter lifetime at high operating temperatures.

    In a similar study on their eWLB package, Infineon finds that the most critical spots susceptible to EM voiding at high current loads turned out to be the terminations of RDLs with transition to the chip pad or the solder ball, respectively. The critical electron flow at the RDL/chip pad interface is the downstream direction since the current densities in the thin aluminum line are much higher compared to those in the thicker Cu RDL. The voiding occurs in the aluminum pad underneath the RDL via followed by liner punch-through. The interface between SAC solder ball and RDL shows a distinct bimodal failure behavior of which the root cause could not be identified. The upstream stress direction turned out to be the critical electron flow direction. The voiding is driven by copper migration and occurs at the very transition between RDL feeding line and solder ball, which is the location of the highest current density, defined Cu/Cu3Sn IMC boundaries and pre-existing Kirkendall voids. A significant boost in lifetime can be achieved by changing the ball pad construction (e.g. thick Cu UBM) or by means of layout optimization (RDL via size, RDL shape).

    Amkor fabricated a special test vehicle to get a direct comparison of Cu Pillar EM with that of various solder bump compositions.  For solder bumps a TiW(1000A)/Cu(1500A)/Ni(2um) UBM stack was used. For Cu pillars, 55um of Cu was plated up on sputtered TiW/Cu. The Cu pillars were then plated with 20 and 40um SnAg solder to form solder caps. More than 8000 hours of testing on flip chip solder bump and Cu Pillar, revealed that Cu Pillars have the best reliability amongst the four bump metallurgies ( vs high Pb ,eutectic SnPb and SnAg ). 5 combinations of current and temperature were used to estimate the current carrying capacity of Cu-SnAg-Cu ?-bumps of 25um diameter. The Cu-SnAg-Cu micro bump structure was tested for 5500+ hours without any failures.

    The EM results for the tested structures is shown below. The data shows lower EM performance for high Pb bumps compared to other bump compositions. High Pb bumps usually considered resistant to electromigration. Published data shows high Pb bump to be better performing than eutectic SnPb bumps. In this Amkor study, the failure analysis showed that the failures occurred on the substrate side with cracks occurring between the Cu-Sn intermetallics and substrate Cu pad. This study used a Cu SOP substrate finish and TiW/Cu/Ni UBM whereas previous data was based on ENIG finish on the substrate and Ti/Ni(V)/Cu UBM. The surface finish turned out to be the main reason for lower EM performance.

    Cu pillar height was varied from 5 to 50um and current density distribution was determined under the pillar. Current crowding is highest with 5um thick pillar with maximum current density on the left side of bump (the side current flows in from). As the pillar height was increased, the current crowding ratio continued to reduce until the pillar height of 35um. A further increase in pillar height, however, started to increase the current crowding ratio slightly. Since lower pillar height is preferred for reducing stresses, Amkor concludes that a 35um pillar height might be optimum for both EM and mechanical reliability.

    IMEC reported on their studies to compare standard NiAu/SAC  (SAC=SnAgCu) solder bumps with Cu pillar bumps in terms of their electromigration behavior. Both bump configurations were flip chipped onto package substrates with a thick Cu finish. The Cu pillar bumps, which are soldered with a thin SnAg cap do not show any significant electromigration damage and do not fail within reasonable testing times and test conditions. IMEC concludes that the rapid formation of a full intermetallic phase is believed to be the main course of the outstanding electromigration performance of the Cu pillar bumps. Standard solder bumps with Ni/Au UBM show a constant failure mechanism of micro-structural degradation through void formation at the interface of the solder and the intermetallics. This occurs for all test conditions used (150-170°C and 300-500 mA).

    TSMC in two separate studies first compared the EM performance of C4 and micro bumps and then examined the EM effects of micro bumps in a 3DIC package.

    1×3 sq mm silicon test chips were populated with the 75-95um diameter SnAg solder bumps which are then mounted on a 12×12 sq mm organic substrate. Surface finishes of both Cu SOP and ENEPIG were studied. For the micro bump EM samples, both  2×3 sq mm and 3×4 sq mm Si on Si stacked packages were used.

    The resistance profiles of the stressed C4 bumps are distinctively different from those of the micro bumps. The early failure commonly observed in the C4 joint is not observed in the micro bump joint. The steady resistance increase in the micro bumps is dominated by IMC formation, which has much higher resistivity than that of Sn [The electrical resistance of Cu-Sn IMC is about 1.5 times more than that of pure Sn, 2.5 times more than that of pure Ni, and 10 times more than that of pure Cu.] There is no obvious void formation from EM stressing even though it has been stressed for a prolonged time with up to 6 times the current density of the C4 bumps.

    TSMC concludes, however "this does not imply that the micro bump joints are immortal for EM. The failure can still occur by Cu consumption when disproportional amount of solder volume and UBM thickness is selected."

    In their second paper EM effects of micro bumps in 3DIC package configurations were examined. Two structures were designed and fabricated: (1) joining of Sn-capped Cu post to ENEPIG (electroless-nickel-electroless-palladium-immersion-gold) UBM pad on silicon substrate and (2) joining of top Cu post to bottom Cu post that forms a symmetrical joint structure (shown below).

    Resistance changes compared to a C4 bump are shown below.

    The resistance shift profiles for both the post-on-post and the post-on-ENEPIG schemes are found to have rapid increase in the beginning and then steadily increment for the long run. TSMC correlates this to the solder wetting on Cu that allows for rapid Cu-Sn IMC formation upon EM stressing, and results in Cu continuing to diffuse for the long stressing period. The resistance change is controlled by the contact area of Cu-Sn interface. Since the solder wetting on Cu enlarges the Cu-Sn contact area, rapid IMC formation occurs. They conclude that "it is very crucial for precise control on the Ni fabricating process as Cu diffusion barrier between Cu and solder to limit the contact of Cu and Sn."

    For all the latest on 3D IC Integration and Advanced Packaging stay linked to IFTLE.........

    IFTLE 55 ECTC Discussions on 3D Processing

    June 21, 2011 9:43 AM by Garrou
    Before we get started in this weeks ECTC topic, I wanted to mention that old friend John Lau from ITRI pulled me aside at the ITRI booth to show me a functional example of the interposer test vehicle that we discussed in IFTLE 52 ("3D and Adv Pkging at ICEP 2011). ITRI had several 3D IC focused presentations at this years conference (see below).
    3D integration continues to receive considerable attention due to its envisioned potential to alleviate or reduce performance limitations in continued CMOS scaling
    Details on 3D Processing Issues
     Effect of Etch Rate on Scalloping During Bosch Etching - ITRI
    ITRI discussed their Bosch Etching process in detail. In general, the higher the etch rates the larger the scallops; for 1μm-dia TSVs, the effect of etch rate on the scallop is very small and the scalloping ranges from 57 nm to 83 nm (etch rate 1.7μm/min - 2.13μm/min); for 10μm-dia TSVs, the scalloping ranges from 107 nm to 278 nm (etch rate 3.5μm/min - 5.8μm/min), for 20μm-dia TSVs, scalloping is sizable ranging from 93 nm to 225 nm (for etch rate 4.2μm/min - 8.8μm/min); for 30μm-dia TSVs scalloping is significant, ranging from 97 nm to 258 nm (etch rate 4.6μm/min - 9.5μm/min); and for 50μm dia TSVs scallop is large ranging from 99 nm to 235 nm (etch rate 5.2μm/min - 11μm/min).
    ITRI lists the following issues to be considered for high quality etching:

    Impact of Slurry in Cu CMP - ITRI
    ITRI discusses the minimization of dishing during the removal of thick Cu plating overburden due to filling TSVs and backside isolation oxide CMP for TSV Cu exposure. In order to obtain a minimum Cu dishing on the TSV region, proper selection of Cu slurries and a  two-step Cu polishing process was developed. The bulk of Cu is removed with the slurry of high Cu removal rate and then the Cu surface is planarized with the slurry of high Cu passivation capability at the second step. The Cu dishing can be improved up to 97% for the 10μm-diameter TSVs on a 300 mm wafer. They reached the following conclusions:
    1. For Cu slurry selections for the wafer front side Cu CMP for TSVs and RDLs, the slurries of high removal rate should go along with that of high passivation capability to reduce the metal dishing. Using the slurry with high Cu removal rate to remove the thick Cu overburden on the field and changing to the slurry with high Cu passivation capability to clean the remaining Cu tends to have a much less metal dishing.
    2. The Cu plating performance affects the metal/oxide dishing/erosion after CMP. Minimizing metal recess or dimple right on the patterns after Cu plating is an important indicator for reducing dishing/erosion after CMP. For TSV plating, transferring from Cu recess to Cu protrusion will lead to a much smaller post-CMP metal dishing.
    3. Wafer edge trimming procedure before temporary bonding and backside grinding reduces edge chipping for the subsequent processes. 0.5 mm edge trimming can eliminate the edge chipping issue for a thinned wafer.
    4. For backside oxide CMP for TSV Cu exposure, low pressure  should be used to reduce edge chipping during processing.
    Selection of Adhesive Materials for Temporary Bonding - ITRI
    Most thin-wafer handling solutions are wafer-support-systems: the wafer to be thinned is temporarily bonded on a supporting wafer with an adhesive and thinned down to the required thickness to expose the through silicon vias TSVs. Thin-wafer handling systems can be classified by the five material solutions [Brewer Science(BSI), 3M, TOK, DuPont and Thin Materials (T-MAT),] available through equipment vendors such as EVG, Suss and TOK.
    The different material vendors provide various temporary bonding and de-bonding methods which significantly influence the material selection, equipment in demand and choice of silicon vs glass carrier. De-bonding processes involve various release methods including : (a) mechanical (TMAT), (b) thermal (BSI), (c) solvent (BSI, TOK), and (d) laser (3M, DuPont). A transparent glass wafer is required to serve as the carrier for UV cure and laser release which costs more than a normal Si carrier.
    ITRI has shared the following conclusions:
    1. Wafer thinning and PECVD-SiO2 deposition are the most critical steps for backside processes in thin-wafer handling making it only necessary to qualify an adhesive for these two conditions.
    2. Backside polymer isolation is suggested to replace the backside PECVD SiO2 step (where possible) to alleviate thin-wafer processing issues.
    3. /span>No obvious change or de-lamination occurred in all the chemical resistance tests for the different adhesive options.
    4. The TTV performance of composite wafers with thinner adhesive has been found to be much better than that with thicker adhesive (100μm. Good TTV control for thicker adhesive still has to be developed.
    Wafer thinning and back side processing  - IMEC
     The temporary bonding approach followed by IMEC is based on Brewer Science WaferBond  HT-10.10. After the HT 10.10 layer shows an average thickness of 16.2μm and a thickness variation of about 1μm across a 300 mm wafer. The wafer is thinned down by back grinding to a thickness typically leaving 57μm Si remaining for a TSV depth of 50μm. The total thickness variation (TTV) of the thin wafer after grinding is in the range of 1.6μm across a 300 mm wafer.

    After thinning, an isotropic dry recess etch process reveals the TSVs while keeping the Cu protected in the oxide liner. The presence of the oxide liner prevents Cu oxidation that could occur during subsequent steps of the process flow. Without any CMP step during nail reveal, the TSV depth variation of about 1μm across the device wafers is measured by high resolution profilometry.
    After nail reveal, a thermally compatible low temperature nitride passivation layer is deposited below 200°C. This passivation layer prevents Cu diffusion through the thin wafer to the FEOL active layers when redistribution layers or microbumps are processed on the backside prior to stacking. A nitride layer was been selected over an oxide layer based on the barrier properties of the 2 materials.
    Metrology and Inspection During Bonding and Thinning - IMEC
    For the in-line monitoring of the 3D wafers in the bonding and thinning module IMEC has examined the SPARK platform from NandaTech which has both brightfield and darkfield inspection capabilities.
    There are several key metrology and inspection (M and I) challenges that need to be solved for successful 3D stacking of dies. The most critical steps have been identified to be TSV depth control, glue layer defects and control of the grinding process.
    In the TSV module the critical metrology needs are measurements of via depth during etch and also detection of voids after via fill. If there are any depth variations over the wafer it translates to TSV height variations and this can become important during the grinding procedure. This depth variation should be feed-forwarded to the grinder so that the grinding can stop at a safe distance from the TSVs.

    During the bonding of the device wafer to the carrier, glue layer defects larger than a few microns become critical. If these glue layer defects are not detected pre-thinning they propagate to the device wafer. Therefore, it is equally important to have the right in-line metrology to detect defects after  bonding which would indicate the presence of glue layer defects.
     During grinding it is absolutely vital to the residual Si thickness above the TSVs so that the TSVs are not prematurely exposed. The basic idea is to use a certain wavelength which will only partially penetrate the Si layer (i.e. lambda= 650 to 750 nm penetrates 1.5μm to 3.5μm) and then scan the wafer. If there is a TSV buried deeper than 3.5μm it won't be scattering light. A map of residual Si thickness above the TSV can be generated from the image.
    A proper feed-forward and a feedback system is necessary between the TSV, Bonding  and Thinning modules to compensate for process  variations.
    Wafer Level Molding for 3D Components - Samsung
    Wafer molding is carried out in the chip-to-wafer process to ensure suitable levels of mechanical strength are reached. The key to wafer level mold processing is the reduction of warpage.
    Samsung has studied material issues  optimized the wafer molding process to reduce warpage.  CTE mismatch between 50um thinned wafer and mold compounds is the primary challenge.  Test vehicles (bottom wafers, top chips) were fabricated on 300 mm wafers. A top chip of 8x8 mm2 size was designed and the bottom chip (including TSVs) was designed to a 12x12 mm2 size with 50um thickness. Before wafer molding, a supporting carrier was attached to the backside of the bottom wafer for wafer processing, backside via exposure and pad finishing. The top chips were then stacked on the wafer. After molding, the carrier wafer was detached and diced. The molded unit device's warpage after dicing was measured by shadow moiré from room temperature to 240°C.

    Molding material modulus, CTE, mold thickness and top chip thickness appear to be the parameters that drive the results. The size of the top chip was the dominant factor for warpage.  Warpage variation was mainly found at the overhang area where no top chip is present, which meant that the mold CTE mismatch was worse than inside the top chip area. Thus, a narrow overhang design is important for wafer molding.
    Mold compound composition also had a strong influence on warpage as shown in the table below.
    Conclusions include:
    1.       Warpage decreased with increasing bottom chip thickness, and smaller chip size. This was directly related to the stresses encountered by the CTE mismatch between the mold material and silicon chip.
    2.       Warpage decreased by decreasing the CTE and modulus of the mold material. Low modulus levels decreased the overall stiffness of the package, which is not desirable given that thin wafers need to be manufactured for the TSVs (usually manufactured to under 100μm depth). The minimum modulus values vary according to the packaging process and infrastructure, which is why careful selection of this value is required.
    3.       Warpage levels can vary for the same mold material type depending on the filler content and resin type. By studying the effects of changing the filler content, it was found that decreasing this quantity improved warpage, as well as affecting the package reliability. The amount of shrinkage during curing of the resin also affected the stress levels in the mold material, and hence the warpage levels as well.
    4.       Additional research is required to reduce warpage levels at room and high temperature to 40μm and achieve the required reliability levels. Package materials needs more investigation.
    For all the latest on 3D IC and advanced packaging stay linked to IFTLE.....
    We are trying the address the typo errors in this blog. Please be patient while we try to locate the cause of these errors ! 

    IFTLE 54 2011 ECTC and Glass Interposers

    June 12, 2011 1:44 PM by Garrou
    Greater than 1000 attendees enjoyed the 2011 Electronic Component Technology Conference [ECTC] in Orlando FL. 342 of 641 submitted abstracts were selected by the program committee for presentation.

    The technical focus continued to be on 3D integration which included  6 sessions and several dozen poster presentations. There were also a large number of submissions dealing with electromigration, the issues and reliability of fine pitch 3D micro joints, and numerous new advanced packaging proposals. We will begin by looking at TSMC and Ga Tech presentations on glass interposers and take a look at the other topics in the following weeks.
    Glass Interposers

    Glass is being examined as  a low cost alternative to the Si interposer. Compared to organic substrates ( ca 15 ppm), glass (3.2-9 ppm) has better CTE match to Si (2.3 ppm). Glass also exhibits excellent surface flatness, dimensional stability, high electrical resistivity and the availability in thin and large panels. The main challenges for glass interposers include:
    - the ability to form ultrafine pitch TSV at high speed
    - thermo-mechanical reliability of copper filled TSVs in glass
    - thermal conductivity of glass (Si>glass>PWB)

    Although the fracture strength of a defect-free glass is high, it decreases dramatically with any surface or bulk defects, which could be caused by processes such as etching, cutting, drilling, or metal deposition.
    TSMC reported on test interposers which consisted of 100 um diameter TSV drilled in 360 um thick glass substrates on 200 – 500 um pitch. The test structures had 1,521 I/O in area array on a 40 x40 mm substrate.

    They found that glass fracture strength decreases with decreasing TSV pitch. Higher via density leads to less cross section area and lower strength is observed. Data scatter is reportedly  due to structural defect s inherent in the glass after processing. They found that coating the glass on both sides with a “thin film material” (which appears to be PI) resulted in marginal improvements (10-20%) in glass fracture strength.

     ANSYS modeling was employed to simulate the material deformation for stress and strain analysis when the package is simulated under temperature excursion. A flip chip BGA with BT substrate was modeled for comparison purposes. Solder material, die thickness, glass size, glass thickness, via diameter, via pitch, PI coating thickness and CTE of glass were all examined as variables. When replacing the BT laminate with glass ( CTE of 8..3 ppm) the deformation of the package increases from 0.15 to 0.27 mm due to the larger CTE mismatch between substrate and PCB. Due to reduced CTE mismatch between die and glass, the maximum stress is reduced by approximately 38% when compared to the organic substrate. The most significant factor appears to be die thickness. Thick Si die introduce higher stress on glass substrate, owing to its increased rigidity which restricts the glass and/or die from deforming to relieve the stress. The CTE of the glass is also important since higher CTE glass induces higher stress to the die. They found that a medium CTE (ca. 8.3 ppm) glass is better for lower die stress.
    The substrate serves as an interposer between low CTE Si die and high CTE PCB. Glass with higher CTE reduces BGA balls stress but is harmful to the Si die and vise versa. Overall, from the TSMC simulations, the medium CTE glass substrate at around 8.3 ppm is demonstrated as the optimal choice for the package structure. Some of the other factors, such as glass thickness, via diameter and PI thickness do not seem to play a significant role to affect the stress of the die, BGA ball or glass.

    A Georgia Tech PRC consortium is also looking at glass as an interposer candidate . The glass substrates (either borosilicate [CTE = 3.8 ppm]or “high CTE” [8.5 ppm] glass) are 180 um thick with 15 um thick polymeric coatings on top and bottom similar to the TSMC construction. The 30 um TSV are either filled or conformal. Panel sizes are currently 150 mm.

    The conformal TSV exhibited similar electrical performance as the filled TSV but are expected to show better thermo-mechanical reliability behavior. Stresses in the polymer layers are higher for thicker layers as expected.
    Electrical properties of the glass interposer were extracted from measured and simulated data on ring resonators [dielectric constant ~ 4.8 and loss tangent ~ 0.002 up to 19.4 GHz. Low insertion loss of less than 0.15 dB at 9GHz was measured for the TPVs in the thin glass interposer.
    For all the latest in 3D IC and advanced packaging stay linked to Insights From the Leading Edge?

    IFTLE 53 One Year Later?. Amkor / TI High Density Copper Pillar Bump Technology

    June 6, 2011 9:52 AM by Garrou
    In late June 2010 Amkor and TI announced that they had qualified and begun production of the industry's first fine pitch copper pillar flip chip packages – shrinking bump pitch up to 300 percent compared to then current solder bump flip chip technology [see IFTLE 23, “Xilinx 28 nm Multidie FPGA, Copper Pillar Advances at Amkor ?”]

    Very little technical detail was released at that time, presumably because of the rumored exclusivity TI was given as part of the joint development program. Full technical details were to be withheld a year till the 2011 ECTC conference, which just occurred this past week. We’ll be covering the overall ECTC technical content over the next few weeks, but I first wanted to focus on the Amkor / TI paper “Next Generation Fine Pitch Cu Pillar Technology – Enabling next generation Silicon Nodes” since we have all been waiting a year for the details which were presented by Curtis Zwenger (Amkor) and Mark Gerber (TI).

    Flip chip technology has traditionally been driven by electrical performance and package miniaturization, with application processors being the primary drivers for mobile phone applications. Traditional solder or Cu Pillar interconnect pitches have been 150um to 200um for both low and high end flip chip applications. Today wafers are routinely bumped at 140 – 180 um pitch with 90 um solder balls in area array. Advanced silicon nodes create challenges to fine pitch (less than 100 um) flip chip interconnects and the corresponding substrate technology. Use of low-k dielectrics, thinner ICs, and package warpage are challenges.

    Migrating from wire bond interconnects to area array flip chip requires a redistribution layer be added to the device to provide the required interconnection pattern. Fine pitch flip chip is compatible with existing in-line and staggered wire bond pad patterns, avoiding the cost for redistribution of the circuit on the die. Amkor claims that 80 percent of their internal studies on converting existing area array flip chip designs to fine pitch designs resulted in a lower cost substrate due to metal layer count reduction and/or body size reduction.

    Fine Pitch Cu Pillar Test Vehicle
    The qualification vehicle was a 559 bump chip on 50 um pitch and a 0.4 mm BGA array coming off the substrate ( 12 – 14 mm PoP body size).

    Qualified design dimensions are shown in the figure below. Composition of the solder cap and the Pb free solder were not identified.
    The primary process development challenge centered on the flip chip attach and bonding processes. For Cu Pillar flip chip with pitches less than 100um, the placement accuracy of the die to substrate is critical to help ensure a high yielding manufacturing process. Amkor found that thermal compression bonding was best suited for fine pitch copper pillar products. Thermal compression bonding, used in conjunction with a pre applied underfill (NCP = non conductive paste). The process flow is shown in the figure below.
    It is important to control the height of the die in relation to the substrate. Pillar height, substrate capture pad height, and die thickness must be controlled to help ensure a stable process. For an over bonded Cu pillar die the solder cap can be squeezed out the sides of the joint causing solder shorts between the pillars.

    The new fine pitch packages were put through standard JEDEC MSL L3 260 ºC un-biased package reliability tests including temperature and humidity, unbiased HAST, temperature cycle level B and high temperature storage tests as well as board-level reliability (BLR) testing (drop and temperature cycle) and biased component-level (CLR) reliability testing.

    Rumors are that Amkor is adding additional fine pitch Cu Pillar capacity for TI and that the process is being transferred to TI who will be putting additional capacity in place for some of their own products. TI has indicated that they are open to licensing the fine pitch Cu pillar technology to others.

    For all the latest on 3D IC and advanced packaging stay linked to IFTLE????..

    IFTLE 52 3D and Adv Pkging at ICEP 2011 and reschedule of 2011 3DIC (Japan)

    May 28, 2011 10:46 AM by Garrou
    The ICEP [ Int Conf on Electronic Packaging] is put on by JIEP (Japan Institute for Electronic Packaging) It is usually held in April every year during cherry blossom time in Japan. I recall that in 1998,when the meeting was known as IMC/IEMT Rao Tummala and I were in attendance. At the “gala reception” we were coerced into joining the entertainment on stage and then I, as the junior member, was further coerced to dress up in a “happy coat” which my granddaughters now know as grandpa’s samuri outfit. (see below).

    At this years conference, John Lau of ITRI gave an excellent invited review on the origins, status and future prospects for 3D IC which includes a must have list of 140 references in the field including his observation that Shockley, inventor of the transistor, actually patented TSV in 1958.

    Lau astutely observes “? using a passive interposer to integrate a few “bullet proofed” chips together (like a MCM) want and are used to doing. The passive interposer becomes the most effective 3D IC integrator. It could be very low cost because we don’t have to dig and fill the holes on the active die. Also we don’t have to thin and metallize the active die. Furthermore we don’t have to temporarily bond and debond a supporting wafer to the active wafer.”
    In another paper Lau and his ITRI colleagues discuss the feasibility of 3D IC for system in package structures. In their test vehicle a assive interposer supports a 4 memory chip TSV stack, an electrical test chip, a thermal test chip and a mechanical test chip to measure stress and warpage . The interposer is 12.3 x 12.2 mm and 100 um thick. The TSV diameter are 10 and 15 um on 40 And 50 um pitches.

    TC Chang from IRTI detailed the use of thermocompression bonding for the joining of Pb free microbumps on 20 um pitch. Solvent and plasma are used to remove the flux residue between he microgaps and a capillary underfill with 0.3 um filler (Namics) is used to fill the gaps.

    NEC, Univ Tokyo and ASET reported on the formation of power regulators (buck converters) which consists of a CMOS LSI including active components and an output filter embedded in the Si interposer.
    Koyanagi and co-workers at Tohoku University described their development of 5 um diameter backside TSV technology. Tohoku is located very close to the site of the Tsunami devastation so I’m sure we all wish them well as they bring their University and their 3D activities back up to speed.
    To develop 5 um backside TSV the chip was supported on a glass or silicon support substrate and thinned down to 15 um by grind and CMP. ~ 1 micron SiO2 was deposited as an isolation layer / hard mask . The TSV were created with Bosch process and then lined with SiO2 (500 nm) . Etching parameters (shown below) were used to control the scallop. The bottom of the insulated TSV were opened by SiO2 etching using the thicker backside oxide layer as partially sacrificial mask for the etching.

    2011 IEEE 3DIC
    The IEEE 3DIC meeting which was scheduled for Tokyo this fall has been moved to Osaka in Jan 2012 due to the tsunami / nuclear disaster that Japan has been recently dealing with. The submission deadline for abstract is September 30, 2011.

    For all the latest in 3DIC and advanced packaging stay linked to IFTLE???.

    IFTLE 51 2011 IEEE IITC 3D Highlights, and IEEE ECTC OSAT Preview

    May 23, 2011 5:31 PM by Garrou
    The annual IITC, sponsored by the IEEE Electron Devices Society was held a few weeks ago in Dresden. Ehrenfried Zschech of the Fraunhofer , John Iacoponi of GLOBALFOUNDRIES and Takeshi Furusawa, of Renesas lled the program committee.
    The conference which was instituted in the mid 1990’s was the premier show dealing with issues of on chip interconnect, especially low K. In recent years it has shifted some focus to 3D integration [ see PFTLE 37, “IITC on the 3D Integration Bandwagon” and IFTLE 10 IFTLE 10 “3D at the IEEE IITC”.

    In this years conference Yann Civale from IMEC shared technical details on the “Thermal Stability of Copper Through Silicon Via Barriers during IC Processing”. The IMEC via-middle process flow results in several high temperature processing steps after TSV fabrication, including a final device wafer sintering step, generally in the 400°C range. As you may recall this was introduced to reduce the impact of copper extrusion [ see PFTLE 125, “ 3-D IC at Ft McDowell” and IFTLE 34 “ 3D IC at the 2010 IEDM”] Thus, it is essential to determine the stability of the TSV Cu-barrier at these temperatures to ensure a reliable integration of 3D TSV in CMOS wafers. IMEC reports that 5nm Ta barriers are thermally stable, while Ti-barriers require thicknesses above 5nm to guarantee their thermal stability.

    Paul Marchal of IMEC presented a “Technology Roadmap and Status” for 3D IC. Marchal indicates that 3DIC technology is now becoming available, that co-optimization of design and procfess technology are required and that one of the remaining hurdles remains mechanical and thermal stress.

    The thermo and Thermomechanical challenges for DRAM on Logic are shown below.

    Interestingly scaling of the TSV diameter will strongly reduce the KOZ (keep out zone) as shown below.

    The combination of microbump and underfill has been identified as the major contributor for stress on thinned die as the shrinking underfill bends the thin die around the microbump. Agreement salso needed on exchange formats and models are required.

    Projections for 2015 include:
    - Silicon wafer thickness : preferably 50 um and holding due to stress and thermal issues.
    - Microbump pitch : 20 um and decreasing for improved electrical specs
    - SV dia / pitch : 5-3 um / 20/10 um and decreasing dia scaling to decrease KOZ, results in AR ~ 20
    Armin Klumpp Peter Ramm and co workers at Fraunhofer EMFT presented their information on  “Reliability testing and Failure Analysis of 3D Integrated Systems“. Their 3D-integrated reliability test chip is a 3-level-stack with a modular layout so several types of stacked devices can be realized, numbered type 1 – 4 with basic functions of the “Bottom”, “Middle” and “Top” layers in the figure below. The larger size of the Bottom chip allows access to the measurement pads, independent of the number of stacked layers. The medium chip having TSV’s and can be tested already in the stage of thinned silicon with the appropriate metal layers on front and back side (type 1). In combination with the bottom chip daisy chains can be realized that include TSVs and assembly pads (type 3). Medium chips with no TSVs, can be tested (type 2), to be able to distinguish between TSV and assembly pad parameters. Type 2 and type 3 are available in parallel as soon as the medium chip is assembled on the bottom one. Adding the top chip forms a three level stack (type 4) with daisy chains including TSVs and two levels of assembly pads. The medium chip serves in this case as feed through for electrical signals. The top chip shortens the electrical path to form a daisy chain consisting of at least two TSVs. The chip lay-out contains several elements including Kelvin structures, DC and RF test structures, daisy chains and TSV’s with dimensions varying from 3-50 um. 3D-integrated test chips were fabricated by application of Fraunhofer EMFT´s TSV SLID technology. The applied 3D TSV process is based on inter-metallic compound (IMC) bonding and TSV formation before stacking. For reliability testing, termal cycling (-55 C° to +150 °C) was performed and additional analysis was done by cross sectioning and plasma-FIB.
    ECTC Preview
    Remember when we all rushed to ECTC anticipating the latest advanced packaging presentations of IBM, Intel, Bell Labs and NEC, Hitachi and Fujitsu ? Well times have changed, and over the last two decades the pendulum has swung towards the OSATS and I think it’s fair to say that Amkor, STATSChipPAC and ASE are now producing more than their share of outstanding papers at every ECTC conference.
    As an example, here is the list of papers that Akor is scheduled to present next week in Orlando.
    "Cu Pillar and µ-bump Electromigration Reliability Comparison with High Pb, SnPb, and SnAg Bumps" presented by Ahmer Syed

    "Advanced Coreless
    fcBGA Package with Embedded High-Dk Thin Film Decoupling Capacitor" presented by GaWon Kim

    "Next Generation Fine Pitch Cu Pillar Technology – Enabling Next Generation Silicon Nodes" presented by Curtis Zwenger and Mark Gerber of TI
    "Issues in Fatigue Life Prediction Model for Underfilled Flip Chip Bump" presented by Ahmer Syed

    "Crack Initiation and Growth in
    WLCSP Solder Joints" presented by C.J. Berry

    "A Study on an Ultra Thin
    PoP using Through Mold Via (TMV) Technology" presented by Akito Yoshida

    "Characterization of Intermetallic Compound (IMC) Growth in
    Cu Wire Ball Bonding on Al Pad Metallization" by SeokHo Na
    Hope to see some of you next week in Orlando. For all the latest in 3D integration and advanced packaging stay linked to Insights from the Leading Edge??..

    IFTLE 50 Words of Wisdom

    May 14, 2011 12:22 PM by Garrou
    50 is a big round number that means IFTLE is nearly a year old here on the SST website. From the data I’ve been shown recently, we have steadily built up readership since last spring to the point that we are now getting ~10,000 readers /month to this site. ??.A sincere thank you for your interest.

    As you know the Insights From the Leading Edge, or IFTLE as I like to call it, focuses on 3D integration and other advanced packaging technologies. We try to keep you abreast of where and when they are introduced and what kind of impact they will have on this field of Microelectronics that we have chosen to be a part of.

    I just spent my 62nd birthday with my granddaughters in Houston. This gives me the opportunity to slip in another picture of the girls which I have already explained I get to do because this is my blog.

    Miss Hanna (left) and Miss Madeline (right) informed me that 62 meant I was an old man. I told them that with age came experience and with experience came wisdom so they should listen to their old grandpa. They both just giggled not having a clue what I was talking about. Certainly we all get older, but do we all get wiser ? I’ll leave that as something for you to think about.
    On my birthday I noticed that Dr Morris Chang had a few words to say in the China Post. Chang, Chairman and founder of TSMC and winner of the 2011 IEEE medal of honor, announced that TSMC is now capable of 28 nm and is focusing on 20 nm. He also announced that Moores Law would meet its demise by 2020 at which point we simply would not be shrinking transistors any more. These were strong words from a man who runs the worlds number one IC foundry. [Link] He pointed out that in the future, more attention will be paid on packaging solutions and printed wring boards which had not yet met their physical limits. For TSMC he pointed specifically to MEMS, image sensors, photovoltaics and LEDs.

    At a TSMC forum April 5th in Santa Clara Chang indicated that the PC and cell phones have been the big drivers for the IC industry but that now “ a third 'killer app. - mobile products (smart phones and tablets)” was ruling things.

    Addressing 3D, Chang indicated that TSMC has poured "significant R and D" into 3-D chips using through-silicon vias (TSVs). The company calls it as a paradigm shift called "systems-level scaling," .
    Looking at the 450 mm waer question he noted that "There are still a lot of challenges for 450-mm," and that TSMC “ would build a 450-mm pilot line in the 2013-2014 time frame, followed by production in 2015-2016” with “the intercept point is 20-nm”

    Some might think that these concepts were put together by his underlings who are assigned to stay on top of technology, but maybe not. Chang has always been keenly interested in both the technology and the business aspects of our semiconductor industry since his early days at MIT.
    My own experience with Dr Chang came about 12 years ago when I was in Taiwan introducing BCB for redistribution and bumping. We were visiting TSMC when our host informed us that the Chairman would be joining our meeting because he wanted to understand what all the of the interest in bumping and redistribution of chips was about. He personally took us out to lunch in order to have more time to absorb technical. He explained that he knew that bumping technology was being used by the mainframe players but had recently been hearing that it was moving into consumer products. A few years later, TSMC became the first foundry to put bumping capacity in place (2001). ??Morris Chang – without question is a wise, old man.

    Intels new “3D technology”
    As if we didn’t have enough trouble explaining that 3D IC technology has nothing to do with wearing glasses to watch your new TV, some reporters in the industry are now calling the Intel;tri gate transistor a “3D chip” [link] . Actually this is not something new, Intel first announced their tri-gate structure in September 2002 and indicated that they were readying it for introduction at 32 or 22 nm, which is exactly what they are doing.
    This concept here is explained very nicely by Greg Crowe [link]. “Here’s the basic idea. A transistor has power flowing through it from the source end to the drain end. The presence or absence of a current is determined by the voltage level of the gate that bridges the two. The major problem with the traditional setup involves signal loss resulting from the fact that the gate only contacts the source and drain on one surface. A tri-gate transistor has three gates that make contact on three sides at once, effectively tripling the amount of surface through which electrons can travel. This produces less data leakage and uses less power than the older design.”

    Intel has indicated that this will deliver a third more processing speed, and about half as much power consumption. This means that at 22 nm Intel can pack in twice as many transistors in about the same-sized chip for the same power usage, which operate a third faster – effectively giving us about 2.5X the processing power for the same power consumption.
    There are those asking how this will affect the introduction of 3D IC. Only Intel knows for sure, but I can tell you that these faster ICs will be looking to access memory even faster than they do now so my guess would be that memory on logic will be needed even more.

    My previous thoughts were that TSV would show up in the 22 nm Intel "ivy bridge" [see IFTLE 38, "..of Memory CUbes and Ivy Bridges..."] with both stacked memory and interposer. We will see whether that is still true.
    So thanks for your continued readership and if you continue to be interesred in 3D IC integration and other advanced packaging, stay linked to IFTLE !

    IFTLE 49 Mentor 3D-IC Test Strategy; GSA Memory Conf

    May 8, 2011 1:09 PM by Garrou
    Before we start this weeks topic, we have some corrections to offer up from IFTLE 48:

    Semi and SEMATECH Lets Get it Straight

    A SEMI representative got in touch to let me know that, while SEMI and some people from SEMATECH work together on 3D-IC standards, the two organizations do not have an alliance on TSV. “Both SEMI and SEMATECH are taking key leadership roles in the discussion and promotion of standards for 3D-IC technology. SEMATECH is working with SEMI on assembling standards committees and task forces. Working with SEMI, SEMATECH's goal is to leverage standards to head-off potential show-stoppers.”

    “SEMI International Standards is very involved in 3D-IC manufacturing standards. The SEMI 3DS-IC Committee was created in late 2010, and has several activities underway in three task forces. The Inspection and Metrology Task Force is measuring the properties of TSVs, the Bonded Wafer Task Force is working on parameters for bonded wafer stacks, and the Thin Wafer Handling Task Force is developing standards for transport and storage. In addition, a new task force to address trimming of device wafers and carrier wafer dimensions is expected to start work at the 3DS-IC Committee’s next meeting on Tuesday, July 12, 2011 at SEMICON West 2011. The committee is currently chaired by Applied Materials, Qualcomm, Semilab, and SEMATECH. [link][link] and [link]

    They also correctly noted that “3D Interconnect Wiki: Stress Management for TSVs” ( ) and the Wiki site ( ) are SEMATECH not SEMI sites.

    Glad you all are paying attention, thanks for the corrections and I hope that straightens it all out.

    Mentor Graphics 3D-IC Test Solution

    Mentor Graphics Corporation recently announced their complete Mentor test solution for 3D-IC, Tessent® v9.4 which will be released May 2011 [link].

    The Tessent MemoryBIST product provides at-speed testing of stacked memory die with support for all popular DRAM protocols, and allows memory parameters (address size, waveforms) and test algorithms to be programmed post-silicon. This allows memory BIST controllers in a logic die to handle a variety of memory die stacked on top for different product variations. The product also supports at-speed testing of memory buses, which covers both bond wires and TSV interconnects. A shared-bus capability enables test of multiple memory die on the same interconnect.

    The Tessent test solution reportedly addresses the three main challenges of 3D-IC testing:
    - the need for higher KGD test quality to ensure acceptable package yield
    - the ability to enable comprehensive testing of all die within a packaged stack
    - the ability to test all die interconnects after packaging

    KGD is addressed by:

    - Support for advanced fault models, including at speed testing in addition to normal “stuck-at” and bridge testing.
    - Test pattern compression, which enables higher test coverage while lowering the cost of test by reducing tester memory requirements and test time.
    - Hierarchical test capability, which simplifies test development and debugging, reduces test time, and allows high coverage even for complex chips, limited by I/O pin count, routing congestion, or, in the case of 3D-ICs, inter die test paths
    - Integration of automatic test pattern generation (ATPG) and built in self test (BIST) techniques to achieve highest coverage at the lowest cost.

    3D-IC Test Challenges After Packaging
    In 3D-IC stacks, each of the die must be re-tested after the die have been packaged to make sure they remain fully functional. Post-package test is the first opportunity to test all the TSV or interposer connections between die for proper connectivity and at-speed performance. For processor and memory stacks, the memory bus interface logic must also be tested at full speed.
    Test point access is a problem because the bottom die is the only one with direct access pins. IMEC has proposed extensions to IEEE 1149.1 (which defines standard test access points0 to allow application of tests in multi-die stacks Their TSV-based 3D test architecture requires supporting methods for routing test data through the stack, and methods to re-sequence test patterns as appropriate for the extended scan chain paths. The Tessent tool suite provides support for implementing the IMEC extensions.
    Tessent ATPG and BIST test products reportedly work together to minimize test development effort and to enable parallel testing to increase test throughput.

    At the GSA Memory Conference last month, Sharon Holt, Sr VP at Rambus reiterated the well known position that smartphone and tablet use is increasing and will overtake standard mobile phone use in 2015.

    When looking at the options for mobile memory moving forward Holt proposes that the industry could continue to evolve todays technology based on low-power DDR2; switch to the newly announced wide I/O memory interface or use the Rambus designed XDR mobile memory solution.
     JEDEC has defined a 512-bit wide interface to increase the bandwidth between memory and logic. The interface operates at a peak data transfer rate of 12.8- gigabytes per second (GB/s), which is up to four times the performance of conventional low-power memory solutions. While Samsung and others have proposed commercialization in 2012 [see IFTLE 36, “RTI ASIP 2010 Part 2 ] and Nokia has indicated that they will see wide IO memory in production in 2013 [ see IFTLE 19, “Semicon Taiwan 3D Forum Part 2” ] Holt indicated that due to the complexity and costs, TSV-based wide I/O DRAM will probably not arrive until ''the second half of the decade’’.

    Yoram Cedar, CTO of SanDisk took a look at flash memory.

    Cedar expects to see a 5X increase in flash usage in the next 3 years :
    Cedar concludes that NAND scaling will need new technologies in ~ 2014 and that “3D Read/Write Memory Will Likely Be the Successor to Floating Gate NAND Flash Over The Long Term” Note 3D here does not refer to TSV technology but rather as shown below.
    Penn State
    Yuan Xie, long time 3D practitioner from Penn State showed that 3D should have significant cost advantages over scaling at the 32 and 22 nodes.

    What are the novel architectural designs enabled by 3D integration ?
    - Latency (fast interlayer interconnect)
    - Bandwidth (high number of connections bw layers)
    - Heterogeneous integration
    - Cost benefit
    What “Killer” applications could benefit from the unique features 3D can bring ?
    - High-capacity memory
    - Multi/many-core ?
    - Exascale computing ?
    Kyowin Jin – Hynix Semiconductor
    Kyowin Jin, VP of Product Planning for Hynix Semiconductor looked at the use of 3d technology in the DRAM industry. 3D TSV technology offers something to the computing, the graphics and the mobile segments of the memory industry.

    Jin showed a Hynix 3D roadmap that shows prototype development for 3DS-RDIMM and for 3DS-DDR3 in 2-11 and ultra wide IO development in 2013 as shown below:

    For all the latest in 3D IC and advanced packaging developments stay linked to Insights From the Leading Edge?????..

    IFTLE 48 SEMATECH Addresses the Reliability Impact of Stress on 3DIC

    April 30, 2011 11:37 AM by Garrou
    The latest SEMATECH workshop “Design for Reliability Workshop – Stress Management for 3D ICs Using Through Silicon Vias”, in collaboration with Fraunhofer IZFP, and chaired by SEMATECHS Larry Smith, was held in March in Santa Clara. The keynote by Prof Paul Ho, U Texas,“Reliability Challenges for 3D Interconnects” served as a tutorial that outlined some of the basic incremental reliability challenges associated with the 3D technology. A presentation “Cu TSV Reliability: Modeling, Test Structures and Measurement Techniques” given by Victor Moroz of Synopsys, summarized some of the experimental work done at IMEC and presented data relating the electrical effects and stress in specific 3D structures. A paper “Thermo-Mechanical Reliability of TSV Packages”, presented by Xi Liu and Suresh Sitaraman of Georgia Tech provided an overview of the 3D state of the art work at package level. Three presentations “Design For Reliability of BEoL and 3-D TSV Structures—A Joint Effort of FEA and Innovative Experimental Techniques” presented by Juergen Auersperg of Fraunhofer, “Role of Thermo-Mechanical Modeling in 3D TSV Reliability Evaluations” by Kamal Karimanal of GLOBALFOUNDRIES, and “3D IC Reliability: A New Frontier” by Raymond Wang of ASE, demonstrated the use of various FEA approaches for modeling 3D structures. The workshop goals was to examine the mechanical stress-driven failure mechanisms, associated test vehicles, and characterization and modeling methodologies which pertain to the via- middle through-silicon-via (TSV) 3D stacking technologies.

    Before I take a look at some of what was presented,  I’ll reiterate that I think readers of this blog come here for 3DIC and advanced packaging insight and part of that insight is knowing the latest spots to retrieve useful information.
    We have previously discussed the SEMI/ SEMATECH alliance that is in place [ see IFTLE 33 “Micron 3D Response, SEMATECH Stds, Leti 300 mmLine” ] Semi has also been developing a Wiki site where important areas in microelectronics are to be discussed [link ] From this page you can access the 3DIC tab which leads to discussions about 3DIC. In addition SEMI /SEMATECH has now started a page [link] which covers “3D Interconnect Wiki: Stress Management for TSVs”. If you get nothing else from this blog, go to these two sites and acquaint yourself with what’s available.

    Paul Ho – U Texas
    Ho has examined the effect of TSV scaling on keep out zone (KOZ) and concluded that the near surface stresses degrade the carrier mobility and thus define the KOZ through the piezoresistivity effect. Defining KOZ as no more than 10% decrease in mobility :

    • KOZ scales with the square of TSV diameter.
    • KOZ minimized at a TSV aspect ratio less than 3
    • KOZ is larger for analog devices than digital devices.

    • The KOZ can be significantly reduced by using annular TSV.
    Victor Moroz – Synopsys / IMEC
    Synopsys / IMEC made a presentation on the characterization and modeling of 3D IC with via-middle TSV. Their studies on copper fill chemistries showed that chemistry “C” had 3X the stress of two other comparable materials. This copper had a finer grain structure and showed little to no grain growth after temp cycling.

    They found no significant change in TSV C-V behavior before and after thermal cycling. When measuring the minority carrier lifetime from he transient response of a MOS capacitor they saw no significant change in TSV C-V behavior before and after thermal cycling.
    After proper thermal treatment to minimize “copper pumping” (copper protrusion) they found no damage to M1 or M2 above the TSV . Examining the impact of TSV generated stress on the transistor performance they found good agreement between modeling and obtained data.

    When examining the impact of Cu/Sn microbumps on N-FET logic devices of dies thinned to 25 um , they found a 40% impact on NMOS current due to he underfill that was being used to reinforce the interconnect bumps. Without underfill, no impact on current was observed. The zero stress temp was found to be ~ 160 C , i.e the curing tem of the underfill (as expected). The explanation is that the shrinking underfill bends the thin die around the Cu/Sn bump generating the observed stress.

    For all the latest on 3D integration and advanced packaging stay linked to Insights From the Leading Edge??


    IFTLE 47 IBM 3D Cooling, TSMC Pkging, UMC 3D Equipment, the CIS Mkt Growth

    April 26, 2011 12:59 PM by Garrou
    IBM water cooled 3D IC At the recent CeBIT Fair in Hanover Germany, IBM CEO Sam Palmisano presented German Chancellor Merkel with a prototype of the IBM 3D Chip Stacking Project developed at IBM Research – Zurich. Merkel asked him, "Did you take that from Intel?" Palmisano reportedly reply, "No, ours are better”.

    [Merkel gets points for pushing IBMs hot button (probably unknowingly) and Palmisano gets points for a sharp response under pressure !]
    German chancellor Merkel and IBM’s CEO Palmisano

    Their 3D chip stacks are cooled by 50 um micro channel cooling technology . Such liquid cooling reportedly reduces power consumption or the normal cooling fans. The cooling technology was developed by IBM together with the École Polytechnique Federale de Lausanne and the ETH Zurich within the scope of the European CMOS AIC project. Dr. Bruno Michel manages the Advanced Thermal Packaging group at IBM Research - Zurich. The group has pioneered energy-efficient hot-water-cooling and the concept of a zero-emission data center.

    The first goal is reportedly to directly stack memory onto the processor. IBM's 3D technology is reportedly scheduled to appear in its upcoming Power8 processor, planned for 2013, using 28 or 22nm process technology. While the technology is reportedly being transferred to iDataPlex servers, it is expected that it will be a few more years before it is fully ready for production.

    ?TSMC Interposer Production in 2012, Making Move into Advanced Packaging

    We first started tracking TSMC’s San Jose spring technical symposium in 2008 when TSVs first appeared on their roadmap [ see PFTLE 30, “Foundry TSVs Are a Comin’ – TSMC Makes Their Play for a Bigger Portion of the Pie” In 2009 they reconfirmed their plans for fab based TSV . [ see PFTLE 73, “ TSMC Reconfirms Plans for Fab-Based TSV “]. At this years meeting, last week, Sr VP of R and D Shang-Yi Chiang indicated that they would initially offer silicon interposer technology, which they are currently sampling and plan to have in full production by late 2012.

    Perhaps more interestingly, TSMC updated the audience on a theme they first brought up in 2008 when they suggested that they might “in the future” be after a bigger portion of the packaging pie. We recently reported that TSMC would enter the interposer technology and that in fact they were delivering the interposers to Amkor for assembly already bumped, rather than have Amkor do the bumping [ see IFTLE 43, “IMAPS Device Packaging Hilights – 3DIC”] TSMC first put in bumping capacity for 200 mm wafers in 2001 when they installed 15K wafers/mo capacity for business with Altera. They have had limited bumping and WLP capacity since then although they have mainly used their OSAT partners for such operations.

    Now TSMC is expanding its bumping efforts. They will ramp up a new 200,000 to 250,000 wafers per month bumping facility in Tainan, are qualifying 100-micron bump pitch lead-free and new copper pillar bump technology at the 28-nm node and are ramping up 28 nm WLP qualification by December targeting the mobile market. Although claiming to still be a “front end company” it is clear to IFTLE that TSMC is making inroads into the packaging business.

    UMC Announces 3D Equipment Aquisition

    In mid 2010 UMC announced their 3DIC alliance program with Elpida and Powertech Technology (PTI). [see IFTLE 8, “3D Infrastructure Announcements and Rumors” ]At that time, UMCs CTO reported that they expected to be sampling 3D IC solutrions using their 28 nm technology “ mid 2011) with production slated for 2012. In keeping with these previous announcements, UMC has just announced that they have acquired $19 MM worth of 3D TSV production equipment from Hong Bao Technology (a 73% owned subsidiary)

    ?CMOS image sensors continue to overtake CCD

    i-Supply reports that in 2011 CIS ( a key applications area for TSV and in the future 3D IC stacking) will surpasses CCD by > 10:1 in both units and revenue.

    Image sensor Shimpents and Revenue (i-Supply)

    CMOS image sensors for digital cameras, the last bastion of CCD technology, are expected to exceed those of CCD devices in 2013. CMOS sensor advantages include lower power consumption, reduced cost and circuit integration. The lower power consumption of CMOS sensors yields longer battery life. CMOS sensors also allow for the possible inclusion of on-chip peripheral circuits, increasing the integration of electronics and reducing the size of DSCs. CMOS sensors also support backside illumination technology (BSI), enabling better quality imaging in low lighting conditions.

    CMOS image sensors shipments for DCS are projected reach ~ 71 MM units, up from ~ 30MM in 2010. CCD shipments are expected to decline to ~ 67 million units in 2013, down from ~ 94MM in 2010. By 2014, more than 85MM CMOS are expected compared to 51MM for CCD.

    Digital still camera image sensor unit shipments by technology (MM of units).

    For all the latest in 3DIC and advanced packaging, stay linked to IFTLE?????????..


    IFTLE 46 3DIC at DATE 2011; Intel’s Paniccia Points to Optical Interconnect ; Applied Continues Move into Packaging

    April 16, 2011 5:31 PM by Garrou
    DATE (Design, Automation, Test – Europe) was held in Grenoble Fr March 14-18.

    Penn State
    Yuan Xie from Penn State and IBM collaborators from the System and Technology Group took a look at 3D IC thermally-aware bus optimization.
    Given that :
    - TSVs are clustered for both signal and power delivery
    - TSVs are duplicated (redundancy as high as 20x) for higher reliability and higher yield
    What is the impact of these TSV clusters on 3D thermal profile ?

    ?They found that large copper TSVs improve the vertical heat dissipation whereas dense and insulated tungsten via farms act as lateral thermal blockage. With the proposed TSV bus optimization flow the peak temperature can be reduced as much as 18.5K and the average temperature reduced by 4.3K.

    Technology Design Forum 
    The Tech Design Forum ( formerly EDA Tech Forum), has been restructured to focus on fast-growing technology markets in specific regions and has added panel discussions of industry and media experts, as well as technical sessions. They will hold the following meetings in 2011:

    March 10 - Santa Clara; April 11 - Tel Avivl; July 20 - New Delhi; July 22 - Bangalore; August 25 - Tokyo; August 31 - Shanghai; September 6 - Beijing; September 8 - Hsin-Chu; September 8 - Santa Clara.

    The March 10th Tech Design Forum "EDA Edition" focused on IC Design and Verification, exploring ecosystem networking and increasing competiveness in IC and system product development. The keynote by Dr. Mario Paniccia, Intel Fellow, titled "Bridging Photonics and Computing" discussed recent advances in silicon photonics, including the first silicon photonics optical link operating at 50 Gbps, the scalability of this technology and its potential applications.

    Intel asks the question “With all the data that is moving and will need to be moved, how do we connect all these devices?

    Paniccia claims that copper is approaching its limits and that optical transfer, which is now mainly used for longer distances, needs to be driven to higher volumes and lower costs to offer a solution for this market .

    They feel this will be achieved first by integrating all the devices on to silicon and then by creating monolithically on a silicon base.

    Applied Continues Move Into Advanced Packaging

    We have previously discussed what appears to be the planned move of Applied Materials into the IC packaging space [ see PFTLE 72, “Samsung 3-D ?Roadmap’ That Isn’t”; PFTLE 41, “3D Integration Stays HOT at Semicon West” ]

    Applied Materials has now signed an agreement with Singapore’s Institute of Microelectronics (IME) to set up a Center of Excellence in Advanced Packaging in Singapore. The Center, to be located at Singapore’s Science Park II, will focus on new capabilities in advanced packaging. When finished, this advanced semiconductor packaging RandD facility will enable IME to support Applied Materials’ product development initiatives. The Centre will have a full 300 mm line of Wafer Level Packaging (WLP) and 3DIC processing equipment and will conduct research in semiconductor hardware, process, and device structures.

    Applied expects many advanced logic devices at the 40nm and below technology nodes to be packaged at the wafer level. Russell Tham, Regional President - South East Asia, said, “This collaboration is to ?. (bring) our development activities closer to our customers in Asia.”

    For all the latest in 3D IC and advanced packaging stay linked to IFTLE......


    IFTLE 46 3DIC at DATE 2011; Intel’s Paniccia Points to Optical Interconnect ; Applied Continues Move into Packaging

    April 16, 2011 5:31 PM by Garrou
    DATE (Design, Automation, Test – Europe) was held in Grenoble Fr March 14-18.

    Penn State
    Yuan Xie from Penn State and IBM collaborators from the System and Technology Group took a look at 3D IC thermally-aware bus optimization.
    Given that :
    - TSVs are clustered for both signal and power delivery
    - TSVs are duplicated (redundancy as high as 20x) for higher reliability and higher yield
    What is the impact of these TSV clusters on 3D thermal profile ?

    They found that large copper TSVs improve the vertical heat dissipation whereas dense and insulated tungsten via farms act as lateral thermal blockage. With the proposed TSV bus optimization flow the peak temperature can be reduced as much as 18.5K and the average temperature reduced by 4.3K.

    Technology Design Forum 
    The Tech Design Forum ( formerly EDA Tech Forum), has been restructured to focus on fast-growing technology markets in specific regions and has added panel discussions of industry and media experts, as well as technical sessions. They will hold the following meetings in 2011:

    March 10 - Santa Clara; April 11 - Tel Avivl; July 20 - New Delhi; July 22 - Bangalore; August 25 - Tokyo; August 31 - Shanghai; September 6 - Beijing; September 8 - Hsin-Chu; September 8 - Santa Clara.

    The March 10th Tech Design Forum "EDA Edition" focused on IC Design and Verification, exploring ecosystem networking and increasing competiveness in IC and system product development. The keynote by Dr. Mario Paniccia, Intel Fellow, titled "Bridging Photonics and Computing" discussed recent advances in silicon photonics, including the first silicon photonics optical link operating at 50 Gbps, the scalability of this technology and its potential applications.

    Intel asks the question “With all the data that is moving and will need to be moved, how do we connect all these devices?

    Paniccia claims that copper is approaching its limits and that optical transfer, which is now mainly used for longer distances, needs to be driven to higher volumes and lower costs to offer a solution for this market .

    They feel this will be achieved first by integrating all the devices on to silicon and then by creating monolithically on a silicon base.

    Applied Continues Move Into Advanced Packaging

    We have previously discussed what appears to be the planned move of Applied Materials into the IC packaging space [ see PFTLE 72, “Samsung 3-D ‘Roadmap’ That Isn’t”; PFTLE 41, “3D Integration Stays HOT at Semicon West” ]

    Applied Materials has now signed an agreement with Singapore’s Institute of Microelectronics (IME) to set up a Center of Excellence in Advanced Packaging in Singapore. The Center, to be located at Singapore’s Science Park II, will focus on new capabilities in advanced packaging. When finished, this advanced semiconductor packaging RandD facility will enable IME to support Applied Materials’ product development initiatives. The Centre will have a full 300 mm line of Wafer Level Packaging (WLP) and 3DIC processing equipment and will conduct research in semiconductor hardware, process, and device structures.

    Applied expects many advanced logic devices at the 40nm and below technology nodes to be packaged at the wafer level. Russell Tham, Regional President - South East Asia, said, “This collaboration is to …. (bring) our development activities closer to our customers in Asia.”

    For all the latest in 3D IC and advanced packaging stay linked to IFTLE......


    IFTLE 45 Interconnect Giants

    April 8, 2011 12:07 PM by Garrou
    I recently read of the passing of Dimitry Grabbe and it saddened me deeply. As time passes those that preceded us are often forgotten and their accomplishments overlooked.

    The Grabbe obituary indicated that he was 83 and had most recently taught at Worchester Polytech in Mass. He was responsible for more than 500 patents in the areas of machine design, semiconductor packaging, electronics assembly and optoelectronic connector design. Dimitry joined AMP in 1973. He was recognized by AMP with a Lifetime Achievement Award, and by the American Society of Mechanical Engineers, which chose him for its Leonardo da Vinci Award. An IEEE Life Fellow, Grabbe was also a fellow of IMAPS.
    In 2007 Grabbe was the fifth recipient of the IEEE Components, Packaging, and Manufacturing Technology award. His citation reads: "For contributions to the fields of electrical/electronic connector technology, and development of multi-layer printed wiring boards."

    Dimitry was part of the group Microelectronic Interconnect Greats that lived in the greater NYC metropolitan area in the days before Silicon Valley. When I was still young and impressionable, Dimitry was already a highly respected “leader of the Pack” along with close friends Jack Balde of ATT (who passed away in 2003) and George Messner of AMP AKZO (who passed away in 1996). With Bell Labs in its “hey day” and IBM Yorktown up the river, some would say that metropolitan New York was the center of the microelectronics universe.

    What separated these three from the rest of the professionals in the area was that they always had time for discussions with younger colleagues like myself. They understood their responsibility to set up and lead meetings on the topics of the day and to help generate the next generation of technical leaders. They were true scientists who had little respect for “managers” and were always ready to share information with all those who would listen. If there was a rumor anywhere in the industry they knew it !

    Some of the greatest meetings I ever went to were local meetings held at the old IEEE headquarters near the UN building in NYC . Grabbe and Messner and Balde were always there learning new things and sharing what they knew. A native New Yorker myself, I was living in Boston at the time and would make up excuses to get to NY to attend these meetings and be around these giants. Grabbe kept a museum of electronic products in his barn in PA. Supposedly he had things in there that no other museum had. Professionals from all over the country were sending him electronic devices knowing that he would take care of them in his personal “museum”. I truly hope all of that has not been lost ! Maybe an IEEE museum in his name would be appropriate? Many colleagues knew that both Messner and Grabbe had immigrated from the old Soviet Union after WWII. Grabbe related to me many times that he had had some problems with the KGB and spent the rest of his life “packing” ?not packaging?but "packing" in the urban context of carrying a handgun in a shoulder holster. For those who did not know this – it was the reason he always kept his jacket on !

    In the early 1992 I got the opportunity to edit the first MCM textbook “Thin Film Multichip Modules” with Messner, Balde and Motorolas Iwona Turlik. A great learning experience on how to assemble and share information. (Little did I know what I would be doing later in life)

    A young Garrou, Iwona Turlik (Motorola), Messner and Balde at the publication of the book Thin Film Mltichip Modules

    Grabbe and Balde also share the fact that they have received the IEEE CPMT Society medal, the highest honor available for packaging and interconnect practitioners. It’s worth looking at the list of winners of this award since these are truly the giants in our packaging field.

    2004 – Jack Balde – ATT

    2005 – Yutaka Tsukada - IBM

    2006 – C. P. Wong – ATT, Ga Tech

    2007 – Dimitry Grabbe – AMP

    2008 – Paul Totta, Karl Puttlitz - IBM

    2009 – George Harman – NIST

    2010 – Herbert Reichl – Fraunhofer IZM, Berlin

    2011 - Rao Tummala - IBM, Ga Tech

    If anyone reading this does not know who these men are or why they won these awards?well you’ve got some reading to do !

    For all the latest on advanced packaging and 3D IC technology stay linked to IFTLE?

    IFTLE 44 JEDEC Standards, Hynix moves on 3DIC and IC Power Rankings

    April 2, 2011 12:33 PM by Garrou
    JEDEC has recently summarized their ongoing standards development work related to 3D-ICs. The following JEDEC committees and task groups are engaged in developing 3D-IC standards:
    - the Solid State Memories Committee (JC-42) has been working since 2008 on definitions of standardized 3D memory stacks for DDR3 . Future DDR4 standards will be implemented with 3D input.
    - the Multiple Chip Packages Committee (JC-63) is currently developing mixed technology, pad sequence and device package standards.
    - a Low Power Memories Subcommittee (JC-42.6) task group is developing standards for Wide I/O Mobile Memory with TSV interconnect stacked on SoC Processors.
    and Reliability

    - the Silicon Devices Reliability Qualification and Monitoring Subcommittee (JC-14.3) is working on reliability interactions of 3D stacks and has released JEP158: 3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Understanding and Evaluating Reliability Interactions.
    - reliability test methods developed by JC-14.1 and JC-14.2 and quality documents developed by JC-14.4 are applicable to 3D-IC packaged and unpackaged evaluations and qualifications.
    Packaging :
    - the Mechanical Standardization Committee (JC-11) has been working since 2010 on Wide I/O Mobile Memory package outline standardization, including a task group focused on design guide creation.
    JEDEC invites interested companies and organizations to participate.
    I have previously expressed my concerns over the lack of transparency in JEDEC standards due to their self imposed rule forbidding revealing authorship [companies and /or individuals] up the standards. [ see PFTLE 128 “3D IC Standardizatio Begins” ] Those concerns still stand.

    Hynix Semiconductor Joins SEMATECH's 3D Interconnect Program
    Hynix the last top 5 DRAM to not have announce plans for 3D IC has become a member of SEMATECH's 3D Interconnect program. Dr. Sung Joo Hong, Head of the R and D Division of Hynix Semiconductor commented that "3D integration offers a path for higher performance, higher density, higher functionality, smaller form factor, and potential cost reduction,?.by joining SEMATECH's 3D Interconnect program and collaborating with industry-leading partners, we expect to play a critical role in accelerating the commercialization of wide I/O DRAM?” Hong reported that Hynix and SEMATECH will address the commercialization challenges facing the industry as it commercializes wide I/O interface structures using TSVs in high volume manufacturing in the next two years.Hynix will be working with IBM, GlobalFoundries, Toshiba, Samsung, Applied Materials, Tokyo Electron, ASML and Novellus as part of the SEMATECH program.

    IC Power Rankings from IC Insights

    Semiconductor industry capital spending is becoming more concentrated, with a greater percentage of spending coming from a shrinking number of companies. As a result, IC industry capacity is also becoming more concentrated, and this trend is especially prevalent in 300mm wafer technology.

    IC Insights has created a “Power Rating” which is determined by each company’s 300mm wafer capacity and its rank in capital spending.

    Overall, IC Insights believes that the top-10 companies in the “Power” ranking will be the primary drivers in adding capacity over the next few years. GlobalFoundries and TSMC get a boost from their currently aggressive capital spending plans and are very likely to add a significant amount of 300mm capacity over the next few years. Among companies ranked between 11 through 22 Renesas, IBM, TI, ST, and Fujitsu are moving to or continuing with a fab-lite strategy. These five companies appear unlikely to add new 300mm capacity in the future. Powerchip, SMIC, ProMOS, Winbond, and Xinxin appear limited by financial where-with-all (e.g.,) or a lack of desire (e.g., Rohm and Panasonic) to add significant amounts of 300mm capacity to produce leading-edge digital ICs.

    With only ten major players in the 300mm capacity space, the customer base for leading-edge IC production equipment has become very narrow. It is likely that IC equipment and materials suppliers will be focused on these 10 companies in the future.

    For all the latest in 3DIC and advanced packaging news and conference updates stay linked to IFTLE?

    IFTLE 43 IMAPS Device Packaging Highlights – 3DIC

    March 26, 2011 10:05 AM by Garrou
    Ft McDowell AZ was once again the site of the IMAPS Global Business Council Meeting and Device Packaging Conference. For a report on last years conference see PFTLE 123,125,126 [link]

    Brandon Prior of Prismark Partners pointed out that 3D TSV will be competing with the incumbent mobile phone 3D packaging solutions, PoP and PiP. PoP lacks the ability to interconnect more than 200 – 300 I/O from memory, but offers ease of test. TSV will offer higher speed and many more connections .

    James Malatesta of Micron presented his perspective on the work of JEDEC committee JC63, the multichip package committee. First PoP changed the landscape as logic suppliers realized that standard top package “memory modules” were requuired for multiple industry supply sources. He also gave an interesting comparison of low power DDR2 [LPDDR2] vs the wide IO TSV technology that is expected to replace it [see IFTLE 40, “Samsung Wide I/O DRAM for Mobile Products?”]

    Sitaram Arkalgud, Director of Sematechs 3D IC program described their current acivities on the U Albany campus. They view their role as helping to :

    • Develop robust technology solutions
    • Assist member company implementation
    • Drive convergence of the materials/equipment solutions

    Sematech has examined the current 3D TSV tool set and come to the following conclusions:

    ?Rosalia Beica of Applied Materials announced that EMC 3D has achieved their goal of less than $150 / Wafer for 3D processing.

    In Matt Nowak, Sr Director at Qualcomm, presentation he asked the question “since the key attributes of 3D IC are: (1)Performance enhancement; (2) Improved power efficiency; (3) Form factor miniaturization and (4) Cost reduction can 3D IC take the place of scaling as CMOS technology appears to be slowing down or stalling out” . He concludes:

    • If performance enhancement and power reduction are the primary motivation, then TSS opens new opportunities for innovative architectural and SW solutions with major improvements possible. But requires Pathfinding and risk taking.
    • If form factor miniaturization is the only motivation, then yes
    •If cost reduction is the primary motivation, then generally the answer is no. However, TSS can provide cost reduction within a window of time for large die sizes on leading edge nodes.
    • If cost improvement from CMOS scaling diminishes in future nodes (due to Adv Litho and FEOL cost), then the window of opportunity for TSS increases.

    Taiji Sakai of Fujitsu made a strong case for why low pitch bonding has moved to copper pillar bumps and wants to move to direct Cu-Cu bonding . The limiting factor preventing that move right now is time/temp required.
    Sakai reports that if the Cu bumps are cut (planed) with a diamond bit a surface Ra of 7 nm is obtained and an “amorphous like layer” is produced at the surface. Forming a monolithic interface is possible at 200 – 250C (30 min) vs the 350C (30 min) required for a CMP’ed surface.

    ?3D Panel Session
    The 3D panel session was put together by Qualcomm’s Matt Nowak and moderated by Applied Materials Paul Siblerud.

    Interposers failing thermal cycling tests

    It was the fall of 2009 that everyone became aware of copper protrusion (or pumping ) as a reliability issue in 3DIC technology. This was discssed extensively in last years IMAPS DPC[ see PFTLE 125, "3D IC at Ft McDowell"] . In the last 12 months many major players confirmed the issue, solutions were proposed and our fears were allayed as to this being a showstopper for 3D IC technology [see IFTLE 6, "Cu-Cu and IMC Bonding Studies at 2010 ECTC"; IFTLE 30, "IEEE 3DIC 2010 in Munich" and IFTLE 34, "3D IC at the 2010 IEDM" ].

    The rumors going around at this years IMAPS-DPC were concerned with interposers reportedly failing thermal cycling (TC) reliability tests. Word has it that when the interposers are populated with unequal size or thickness silicon chips or stacks the stresses generated on the interposers is so significant that it causes interposer fracture. I asked the panel, which I was part of, to comment on these rumors. Ron Huemoeller, VP of 3D packaging for Amkor answered that this indeed was the case, that they had seen such problems in the Xilinx scaleup. The good news from Ron is that they were able to engineer around these issues. FYI, recall that the Xilinx interposer is 100 um thick. It is unclear from the current rumors at what thicknesses (chips, stacks and interposers) these issues are seen.

    Underfill with Interposers

    Underfill has been around since Tsukada told us that they allowed bumped chips to reliably be used on laminate substrates back in 1992. Thus, one would think that underfills would not crop up as a problem in todays 3D technology. However, you must recall that for something like the Xilinx structure [see IFTLE 28, "Xilinx 28 nm Multidie FPGA..." we are talking about microbumps on 45 um pitch, not your typical 150 um solder bumps on 400 um pitch. Amkors Huemoeller comments on the 3D panel that the underfill process took a year get to a manufacturable state. Hopefully the underfill supplies now have the formulations set and can recommend solutions that can be implemented much quicker than that.

    Phil Garrou (representing Yole Developpment), Ron Huemoeller (Amkor) Eric Strid (Cascade Microtech), Matt Nowak (Qualcomm), moderator Paul Siblerud (Applied Materials)

    EMC 3D closing down??.

    Paul Siblerud of Applied Materials gave the conference pre notification that EMCD 3D consortium members have concluded that they have met their goals and will be closing this summer. Their last presentation as a group is expected to be at Semicon this July.

    Memory Stack Usage coming soon
    Huemoeller offered the following Amkor roadmap for memory stack usage:

     Representing Yole Developpment I offered the following slide as representing the major 3D IC announcements in the past 12 months.
    And the following chart to summarize active major players and their expected timelines for interposer and stack introductions.

    The Latest on Xilinx FPGA Production with TSV Based Interposers

    At the GBC, Suresh Ramalingam of Xilinx discussed the key role of supply chain collaboration. The FPGA is basically a programmable SoC of logic, memory and analog circuits.
    Customers were asking for more logic capacity, more high speed transceivers, more processing elements and more memory and Xilinx was faced with the reality that yield of the devices is directly proportional to device size. Rather than try to interconnect smaller devices on a PWB or MCM, which did not offer enough I/O and resulted in high latency and high power usage, their preferred solution was to connect FPGA “slices” on a silicon interposer which offered massive low latency interconnect (10K routing connections between slices with ~ 1ns latency) and low power consumption. They claim this gives them a 1.9X advantage over their nearest competitor.

    The 28nm Virtex-7 SSIT will reportedly use TSMC fabricated 100µm thick silicon interposers with 10 – 12 µm Cu TSV and 65nm interconnect. The micro-bumps are Cu-SnAg alloys at 45µm pitch.

    The supply chain they put together includes TSMC, Ibiden and Amkor as shown below.
    Mike Kelley, Sr Dir of Advanced 3D Packaging for Amkor indicated that Amkor bumped the FPGA chip wafers whereas the interposers from TSMC arrived bumped and ready for assembly.

    Amkor offered the following process flow for test during assembly :

    For all the latest in 3DIC and advanced packaging news stay linked to IFTLE.............




    IFTLE 42 IMAPS Device Packaging Conference – Fan Out and Embedded Packaging

    March 20, 2011 4:36 PM by Garrou
    Ft. McDowell AZ was once again the site of the annual IMAPS Global Business Council Meeting and Device Packaging Conference. [For reports on last years conference see PFTLE 123,125,126]

    Fan out and Embedded Packaging

    Andy Strandjord and Linda Ball put on an excellent panel session on fan out and embedded technology.
    John Hunt (ASE), moderator Linda Ball (Freescale), moderator Andy Strandjord (Pac Tech), Thorstern Meyer (Intel Wireless [formerly Infineon]),Tom Strothman (STATSChipPAC), Lars Boettcher (Fraunhofer IZM), Navjot Chhabra (Freescale)

    Thorsten Meyer one of the developers of the Ifineon eWLB fan out technology informed the audience that his group is now part of the Intel purchase of the Infineon wireless business. They are now the stand alone business “Intel Mobile Communications” Infineon retains rights to non wireless applications. Anyone wanting to license the technology moving forward will have to license from both parties.

    Navjot Chhabra (recently from the Sematech ultra lowK program) is now Director of the Freescale RCP fanout technology. They are currently running a 200 mm engineering line while licensee Nepes has a 30 mm line running in Singapore. [see IFTLE 25, “IMAPS Part 2: Advanced Packaging] He indicates that qualifications for “?industrial and automotive products are ongoing”

    Meyer also reveled that IZM had licensed their embedding technology (shown below) to Infineon.

    Tom Strothman of STATSChipPAC indicated that eWLB is today less costly than FcBGA. STATS is currently running a 300 mm line for production of eWLB.

    The panel made the interesting comment that both the fan out and embedded technologies were capable of 0.3 mm pitch but that drop test reliability would go down because the UBM cross section would be smaller.

    John Hunt of ASE indicated that ASE does not have 300 mm eWLB in production but commented that “..demand just does not warrant putting that capacity in place” . It was news to me, and I’m sure it will be to most of you, that Infineon is the only commercial customer for eWLB today. Reportedly ST Micro is close but today it is only Infineon .

    Much has been made of the possibility for eWLB to move to panel production. Having tried to do thin film packaging on 450 mm panels at Micromodule Systems in the mid 90’s (see fig below) I know that this is easier said than done. (FYI that’s AVX’s Bob Heistand 3rd from the left on top row, Intels Mike Skinner to the right of me and Larry Moresco in front of him. MMS program Mgr Chung Ho was absent from the

    While all of the eWLB licensees are proposing fan out packaging on panels Hunt commented that “?we (ASE) are actually the only ones who have tried to do this?.If we move forward with this approach it will require a totally new materials set” Hunt also indicated that they are attempting this work on ¼ panels not full PWB panels and obviously they cannot use MUF (molded underfill) to encapsulate the large substrates.

    Next week we will look at a summary of 3D activity at the IMAPS DPC

    For all the latest in 3DIC and advanced packaging information stay linked to Insights from the Leading Edge?.


    IFTLE 41 SRC Focus Center 3D Update

    March 12, 2011 5:15 PM by Garrou
    Founded in 1998, the Focus Center Research Program (FCRP), is one of three research program categories of the well known Semiconductor Research Corporation (SRC) [link]. FCRP research is always looking long-term and big-picture, seeking breakthroughs that are “critical to U. S. security and economic competitiveness”. FCRP programs involve 41 universities, 333 faculty and 1215 doctoral graduate students. The Focus Centers themselves are not physical locations, but rather consist of multiple universities which engage the leading experts at the participating institutions. Each Center is managed by Center Director and addresses one of the major technology focus areas of the International Technology Roadmap for Semiconductors (ITRS).
    The SRC runs 6 “focus centers” (below). All 6 centers believe 3D is important and are working in the area. On Feb 11th the first cross center 3-D workshop was held.
    Tanay Karnik of Intel examined 3Dintegration from the perspective of a processor company. IFTLE has discussed the requirements for low power high bandwidth memory in several recent blogs [ see IFTLE 38, “of memory cubes and Ivy Bridges” and IFTLE 40, “Samsung Wide I/O DRAM for Mobile Products?”]. The slide below shows the bandwidth required to stay on the roadmap.

    When examining thermal issues Karnik emphasized that thermal floorplanning was necessary to insure that thermal hot spots are not aligned as shown below.
    In addition thermal TSV will likely be needed to carry heat directly to the heat spreader as shown below.
    Jerry Bartley of IBM 3D opportunities and prerequisites to deployment. Bartley gave the following standard IBM list as 3D IC advantages:
    Bartley sees an evolutionary path whereby the via diameter, via pitch, number of layers, complexity of the layers, will systematically improve with time. As we have repeatedly said here at IFTLE, Bartley sees “?3D adoption within any application will happen as the technical risks are mitigated and clear cost and performance advantages emerge”

    In agreement with Intels Karnik, Bartley points towards to thermal awareness as a necessary prerequisite for 3D design as shown below.
    ?Bartley sees 3D optimization requiring “3D thinking and system level thought processes” and lastly asks the question that a lot of us are struggling with “Is it a chip or a package ?”

    Andrew Kahng of UC San Diego reviewed IRTS technology working groups which are involved with 3D technology. IFTLE has recently reviewed the same material [ see IFTLE 16, "The 2009 ITRS Roadmap.."] As an example of some of the things being looked at Kahng pointed to the prober challenges we are expected to see after 2013.
    Paul Franzon from North Carolina State discussed he design of 3D systems. Franzon also identified memory on logic as a key driver for TSV based 3D architecture with examples such as high end mobile graphics synthetic aperture radar. When examining the advantages of 2D vs 3D for the synthetic aperture radar application we can see that 3D has significant advantage.
    Muhannad Bakhir from Ga Tech focused on liquid cooling for high performance 3D systems. While the thermal impact of micro channel cooling can be significant, the space occupied by the liquid cooling channels is not insignificant and will limit the thinness of the strata.

    For all the latest information on 3D IC and advanced packaging stay linked to Insights From the Leading Edge??.


    IFTLE 40 Samsung 3D IC Wide I/O DRAM and Semiconductor Predictions for 2011

    March 4, 2011 9:52 AM by Garrou
    Samsung wide I/O DRAM for Mobile Applications

    Samsung, who first revealed 3D TSV stacked memory prototypes in 2006, announced 40nm 8GB RDIMM based on four-gigabit, 1.5V, 40 nm DDR3 memory chips operating at 1,333MHz and 3D TSV chip stacking technology in Dec of 2010. Samsung claimed the 3D TSV technology saves up to 40 percent of the power consumed by a conventional RDIMM and improves the memory chip density. This DRAM chip was suggested for servers to reduce power consumption and save space. They said Samsung planed to apply the higher performance and lower power features of its TSV technology to 30nm-class and finer process nodes.
    At the recent plenary lecture of Dr Oh-Hyun Kwon, President of Samsung ?s semiconductor business, at IEEE ISSCC 2011 (Int Solid State Circuits Conference), he announced the development of wide I/O 1 Gb DRAM. This memory is reportedly aimed at mobile applications like smartphones and tablet computers. Kwon reports that the 3D TSV architecture will be implemented on their 50 nm node DRAM technology. In related disclosure at the ISSCC Samsung researchers offered more details about the wide I/O memory chip in their technical presentation entitled “ A 1.2V 12.8 Gb/s 2 Gb Mobile Wide I/O DRAM with 4 x 128 I/O Using TSV Based Stacking”.
    Previous generations of mobile DRAMs used a maximum of 32 pins for I/O. The new wide I/O solution which has 512 I/O (up to 1200 total) pins can transmit data at a rate of 12.8-Gbytes per second resulting in a significant improvement in processing power. In addition it reportedly reduces the power consumption by 75% by reducing load capacitance. It is expected to replace low power DDR2 DRAM (LPDDR2) which runs at approximately 3.2-Gigabytes per second according to Samsung.

    Following this wide I/O DRAM launch, Samsung is aiming to provide 20nm, 4Gb wide I/O mobile DRAM sometime in 2013. Traditionally "wide" parallel interfaces have been more expensive to manufacture and package. Samsung claims, however, that its 1Gb memory chip with wide bandwidth can be installed instead of a larger amount of smaller chips which results in reduced costs and higher performance.

    The die area is 64.34mm2, about a 25% increase when compared with 1Gb LPDDR2. This comes mostly from the increase in number of circuits to support 4-channel and 512-DQ feature. The whole chip is made up of 4 partitions which are symmetric with respect to the chip center, and each partition consists of 4×64Mb arrays, peripheral circuits and microbumps. To reduce power consumption in 512b I/O operations and to support high data bandwidth, I/O driver loading is reduced by adoption of 44×6 microbump pads per channel, which are located in the middle of the chip. The microbumps are 20×17?m2 on 50?m pitch. A fabricated TSV has 7.5?m diameter, 0.22 to 0.24? resistance and 47.4fF capacitance.

    Semi ISS

    The SEMI ISS meeting (Industry Strategy Symposium )[link] is an annual January event in Half Moon Bay, CA where industry experts and other economic prognosticators make predictions about the upcoming year for the semiconductor industry. [ see PFTLE 121, “IC Consolidation, Node Scaling and 3D IC” for last years coverage]

    Bill McClean of IC Insights pegged the 2010 semiconductor market at $313.8B, an increase of 32% over 2009. He is predicting a 10% increase for 2011. He claims a 98% increase in capex occurred between 2009 and 2010 and projects a 6% increase in 2011 to $53.8B. The semiconductor materials market saw a 24% increase between 2009 and 2010 to $42.9B and will see a 8% increase in 2011.

    When looking at capex by region (2011 projected vs 2005) we see NA holding constant, Japan and Europe going down while Taiwan and Korea are going up.

    10 companies held 85% of the worlds 300mm capacity in 2010.

    ?Handel Jones of IBS predicted the following :

    - 28.1% semiconductor growth in 2010 to be followed by 7.4% increase in 2011. He predicts the next downturn will be in 2013

    - 32 nm is in high volume at Intel and 28 nm is ramping at the major foundries, i.e TSMC, Samsung, Globalfoundries

    - Intel will ramp 22 nm in 4Q 2011, others ramping in 2012 or 2013

    - process technology development is concentrated into a declining IDM and foundry vendor base

    - roadmaps past 22/20 nm are unclear

    - IC vendors are migrating into providing system level solutions

    - A number of significant companies are making significant expenditures in 3D TSV technology with memory on package being a key driver

    When looking at growth by geographic region IBS sees China becoming 50% of total consumption by 2012-2013. This means foreign supply will remain a significant portion (ca. 90%) of consumption out into he future (2015)
    Reitterating his prediction of last year [ see PFTLE 121, “IC Consolidation, Node Scaling and 3D IC” for last years coverage] Jones still sees only Samsung , Intel and maybe ST Micro as IDMs with their own 22 nm logic lines. The reason for this is again explained in terms of the “cost of developing the next generation process technology” as shown below.
    For the first time since we have started following the scaling roadmap, Jones sees an increase in cost / gate at the 22 node.?
    Thus at 28 and 22 nm taking cache off chip into a 3D technology may be a viable economic option.

    For all the latest in 3D integration and advanced packaging stay linked to IFTLE??.

    Hope to see many of you at the IMAPS Device Packaging Symposium in AZ next week !



    IFTLE 39 Packaging Roadmaps at MEPTEC

    February 25, 2011 10:36 AM by Garrou
    In November of 2010 MEPTEC (Microelectronics Packaging and Test Engineering Council) : a trade association of semiconductor suppliers and manufacturers)[link] brought together a group experts from AMD, Altera, Amkor, ASE, Cisco, LSI, Micron, TechSearch, Unisem , Yole and others to discuss the status of Semiconductor Packaging Roadmaps. While the presentations themselves may have had more meat on the bone, many of the handouts were short on data and long on marketing fluff or are materials that we have already recently covered. There were, however, a couple of presentations worth looking at.

    Bill Bottoms, CEO of 3MTS gave the introductory talk taking a look a collaborative roadmaps and international roadmap perspectives. From his position as chair of the ITRS (Int Technology Roadmap for Semiconductors) packaging and assembly TWG (technical working group) Bill reminded attendees that ITRS is sponsored by Europe, Japan, Korea, Taiwan and the US to:

    - forcast semiconductor technology requirements 15 years out and
    - forcast emerging semiconductor devices and materials 10 years out

    Its relationship to other Microelectronic roadmap activities in the US is shown below where i-NEMI is actually the pivot point for all the microelectronic activities.

    On a global basis, the other organization looking at overall semiconductor packaging solutions is JISSO [link], a Japanese term which reflects the total packaging solution for electronic products. The chart below shows its relationship to other global standards organizations.

    Bottoms premise is that for the past 40 years semiconductor progress could be easily predicted. The focus was on design and fab. Semiconductor roadmap goals were all clearly focused on shrinking geometries (scaling) and increasing wafer size. However, as we enter the “deep submicron” era, however, things become more complicated and packaging becomes a more important in delivering semiconductor yield, reliability and performance.

    The answer developed to adress the historical lack of package scaling to match IC scaling was to generate the packaging at the wafer level, i.e. wafer level packaging or WLP. WLP, now firmly entrenched as a packaging option offers portable consumer products :

    - inherently lower cost
    - better electrical performance
    - lower power requirements
    - smaller size

    Several architectural variations of WLP are in use today as are shown below.
    Another important trend in packaging is the incorporation of multiple die into a single package or what has become known as System in Package (SiP) [ MCM to those of us that have been around awhile].
    Moving forward, Bottoms predicts, as many of us do, that the 3rd dimension will be the key enabler in maintaining the “price elastic growth of the electronics industry”. While 3D presents many challenges they all appear to have reasonable solutions. 3D will appear first through silicon interposers with through wafer connections and then through chips fabricated with internal TSV for through wafer connections .

    Bill updated attendees with where the packaging roadmap would be increasing and expanding coverage in 2011. [ see “Packaging, assembly changes coming in next ITRS Update” ]

    Bottoms concludes that the pace of change in packaging technology has never been greater and roadmaps are critical to continuation of this rate of progress.

    Bryan Black of AMD looked at why 3D is required if semiconductor technology is to continue to move ahead. In standard fashion Black defines 3D technology in two varieties as shown below, TSV in active devices and TSV on interposers.

    From a systems standpoint Black proposes the interesting perspective that performance density drives new form factors, new form factors discover new usage models and without new form factors the industry would stagnate. This trend is shown in the slide below:

    For all the latest on 3D integration and advanced packaging stay linked to IFTLE?..




    IFTLE 38 ...of Memory Cubes and Ivy Bridges - more 3D and TSV

    February 19, 2011 1:33 PM by Garrou
    The 3D TSV announcements keep coming at a “fast and furious” pace and are becoming hard for all of us to keep up with. One announcement (this past week) and one rumor, are very important for the forward momentum of 3D IC integration.

    A few weeks ago Mark Durcan, COO of Micron, at the IEEE ISS meeting in Half Moon Bay, commented that Micron is ''sampling products based on TSVs” and that “Mass production for TSV-based 3-D chips are slated for the next year or 18 months'' [see IFTLE 33, “ Micron 3D Response, Sematech Standards, Leti 300 mm Line” ]

    Now, Micron has announced that it is using TSV technology to address the longstanding problem referred to as the "memory wall". [see “Micron to reveal tech it says increases chip speed 20-fold” ]

    For those that are interested, the seminal paper in the area appears to be “Hitting the Memory Wall: Implications of the Obvious” by Wulf and McKee in the March 1995 issue of Computer Architecture News which can be read here [link]. It presents an interesting discussion of the bounds on processor performance imposed by memory performance. Historically, processor performance has improved by about 60% per year, whereas the corresponding improvement in memory access time has been less than 10% per year. Latencies are dominated by DRAM access times which has changed VERY slowly over last 20 years. DRAM performance is constrained by the capacity of the data channel that sits between the memory and the processor. No matter how much faster the DRAM chip itself gets, the channel typically chokes on the capacity. Systems are not able to take advantage of new memory technologies because of this latency issue.

    Brian Shirley, vice president of DRAM Solutions at Micron claims that their “hyper memory cube” technology “?offers a 20-fold performance increase while reducing the size of the chip and consuming about one-tenth of the power”. They reportedly accomplish this by stacking memory on top of a controller layer (shown in the Micron fig below as logic layer) and connecting with TSV. The “wide bus” from the controller layer to the CPU is reportedly “hugh” (possible 512 bits ??)

    Shirley commented “Performance needs are most dire in networking and cloud computing. One-hundred gigabit Ethernet routers and switches and cloud computing servers require everything they can get??this is our way of giving them a fire hydrant.”

    They hope to see the memory cube technology in server and networking markets as early as 2012, with significant volumes in 2013, and could then start to work their way toward the consumer space in 2015.

    The overall concept of the control layer reminds IFTLE of the structures that Bob Patti of Tezzaron has been showing for the past 5 years (see below)

    The Intel Ivy Bridge Processor is the 22 nanometer die shrink of the 32 nanometer Sandy Bridge which is expected to be commercialized in late 2011 or early 2012. Ivy Bridge is expected to pack low-power, low-speed, but large bandwidth memory (some report up 512 bits).

    Although Intel will not confirm, rumors persist that the key to Ivy Bridge’s reported performance is its stacked memory and silicon interposer [see: “Intel puts GPU memory on Ivy Bridge” ]

    Rumors are that Ivy bridge will use LPDDR2 memory, possibly with a speed of only 1066MHz, and that memory stacking technology could bring it up to 1GB. The memory is then stacked upon a silicon interposer. The reason a silicon interposer is essential for Ivy Bridge is the large width of the low-power memory. Since 512 bit brings with it high pin and trace counts, which would require more layers and increase cost. The interposer decreases the required on chip layers and reducing the overall cost.

    IFTLE has taken the rumors a step further. IFTLE thinks it is possible that the following patent application [ see: US 7,841,080 B2 ] entitled “Multichip Packaging using an Interposer with Through Vias” which describes having a CPU on an interposer with stacked DRAM and a voltage regulator may be related to the Ivy Bridge implementation.

    Ivy Bridge may be Intel’s first product introduction with TSV. We’ll know for sure one they release the information and/or once Ivy Bridge is released and analyzed by someone like Chipworks.

    One additional comment. It is likely that the use of an interposer (if true) reveals that Intel agrees with Xilinx [ see: IFTLE 23, “Xilinx 28 nm Multidie FPGA?” ] and indeed true 3D stacking (memory directly bonded to logic circuits with TSV) is not yet available and/or ready for “prime time” ?.yet.

    For all the latest in 3D integration and advanced packaging stay linked to Insights from the Leading Edge?.


    IFTLE 37 Advanced Packaging at Singapores EPTC

    February 12, 2011 2:22 PM by Garrou
    Like the IEEE ESTC meeting held in Europe [see IFTLE 26 Adv.Pkging at the 2010 ESTC] , Asia’s IEEE EPTC meeting, held every year in Singapore, is a sister meeting of the IEEE ECTC.

    The recent interest in electromigration is due to a number of issues including the drive to Pb free bumps, the trend towards increased IO density resulting in smaller and finer pitch bumps, and the introduction of 3D IC structures. The concurrent increase in power density is requiring chip-to-package interconnect to carry more current per interconnect. Since electromigration reliability is a direct function of interconnect dimensions and metallurgy, any new interconnect developments need to be characterized for electromigration reliability.
    Solder composition and under bump metallization (UBM) are key factors that are known to affect electromigration failure. It is well known that increasing current density has a negative impact on electromigration. Reduction in bump size leads to an increase of current density with current density increasing as a square function of the bump diameter.

    Yoo of Nepes reported on their investigation of the impact of UBM (under bump metallization) on electromigration for copper pillar bumps (CPB) and various UBM metallizations (Cu 5?m UBM, Cu 10?m UBM, Cu/Ni UBM ) in conjunction with SnAg solder bumps of various sizes, at a constant current density of 5.09x104A/cm2.
    MTTFs, obtained from Weibull plots are summarized in the Table below. MTTF (20% resistance increase) became longer as test temperature was lowered for each bump structure. At 150 C, MTTF followed the order: CPB > Cu/Ni > Cu 10?m > Cu 5?m. Life time of CPB was 35times longer than Cu 5?m UBM/solder bumps under the same conditions.

    Syed of Amkor shared their studies on the factors affecting electromigration and current carrying capacity of flip chip and 3D IC interconnects. The figure below shows a Weibull failure plot for 700mA, 150C condition. High Pb failed first followed by SnPb and then SnAg bumps. As of 10,000 hrs no Cu pillar EM failure had occurred indicating the Cu pillar bumps performed much better than the other solder bump options tested. High Pb bumps are normally considered very robust in terms of electromigration performance but in this case the surface finish of the substrate is copper SOP (solder on pad) rather than the previously studied ENIG finish.

    Fan out or embedded wafer level packaging (e-WLB) remains a red hot packaging topic only rivaled by 3D IC. [ see IFTLE 22, “Sources for Fan Out WP Continue to Expand” ] In the opinion of IFTLE, FO-WLP is this decades BGA and we will see it replacing the BGA format in many application spaces. While the last decade saw the explosive growth of fan in WLP, FO-WLP takes over as a WLP technology when the package size must be larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects.

    One of the most well known examples of FO-WLP is the “eWLB” developed by Infineon and there consortium consisting of ST Micro, STATSChipPAC and ASE.

    STATSChipPAC presented data on thermal electrical and mechanical performance. In the table below we see that thermal modeling shows that an eWLB and an equivalent FC-BGA show equivalent thermal performance.

    The figure below depicts Q performance comparison of inductors made by different processes/options. An inductor made directly above an active IC has a Q peak is around 26. The same inductor made from the STATS thn film IPD (integrated passive device) process has a Q max of~ 30 whereas if made on mold compound in the FO area, its peak Q can be 35.

    The figure below shows comparison of parasitic values of RLC for fcBGA and eWLB at 1GHz. For resistance, eWLB has 68% less value than fcBGA. Moreover, eWLB has 66% less inductance value and 39% less capacitance compared to fcBGA. It is mainly due to shorter interconnection in eWLB.
    The two main challenges of eWLP are die shift and warpage of the molded wafer. Die shift will impact the alignment of the RDL on the pad of the die and thus the larger die shift drops the yield of RDL tremendously. The encapsulated eWLP wafer need to be handled by various equipment such as an in-line track for passivation or photoresist coating and development, a mask aligner for patterning the passivation or photo-resist, and a sputter for the metal deposition process. The equipment does not accept the molded wafer if its warpage is too high. Themo-Moire technology was used for measure package warpage with temperature profile. There was study of warpage behavior with different material combinations of dielectrics and molding compound material. They note that proper selection of the mold compound and the in-depth understanding of the molding process conditions will definitely minimize the warpage of the molded wafer.
    Multi-die eWLB packaging technology has become a necessity to embed different functionality dies into a single package, especially for wireless and mobile phone applications. The key challenges in processing multi-die packages are:
    1) change in die positions due to thermal expansion of carrier during molding and shrinking of mold compound upon cooling                                             2) warpage of the reconstituted wafer due to presences of multi-dies and “chip to package” ratio                                                                                   3) filling of mold compound in the narrow gap between dies and                   4) Meeting package and board level reliability requirements
    In Rf applications such as power amps (PAs) , the PA chip and a IPD can be combined into a 2 die eWLB as shown below.
    ST Micro, STATSChipPAC and Infineon gave a presentation on the next generation eWLB concepts. They listed the next generation variations of the eWLB as:

    1) enabling two or more layers of routing
    2) expanding the package size to 12x12mm
    3) allowing for thinner packages and side by side chips within the eWLB
    4) double sided Package on Package (PoP) eWLB

    With optimized design, 12x12mm eWLB successfully passed 500 cycles of TC [40/125C, 2cycles/hr.).
    Thinner packages can provide better board level reliability as well as lighter and thinner profile at the system level. eWLB can be thinned down to 250 um thickness. The critical technical challenges included handling the thin wafer and grinding and removing of the Si/epoxy material together using the same process steps. There was found more than 60% increase in thermal cycling performance with thinner eWLB and drop reliability also improved significantly.

    Another approach will be double sided interconnection reminiscent of the Amkor TMV structures as show below.

    For all the latest in 3D IC and advanced packaging technology stay linked to IFTLE, Insights From the Leading Edge?.



    IFTLE 36 3D IC at the RTI ASIP part 2

    February 4, 2011 12:09 PM by Garrou
    Continuing our look at activities at the RTI 3-D Architectures for Semiconductor Integration and Packaging Conference ( 3D ASIP) held in Dec 2010 in Burlingame CA.
    Hiroaki Ikeda (Elpida), Tae-Je Cho (Samsung) and Mitsumasa Koyanagi (Tohoku Univ) discuss the future of 3D IC technology with IFTLE’s Garrou
    Sungdong Cho – Samsung

    Songdong Cho, Sr engineer in the Samsung system LSI group spent the conference besieged by questions from attendees on the Samsung (memory group) announcement that occurred the day before the meeting. [see IFTLE 27, “The Era of 3D IC Has Arrived with Samsung Commercial Announcement”]

    Cho first led the attendees through the evolution of Samsung 3D IC technologies:

    - 2006 Samsung announces memory stacking technology

    -2007 DRAM stacked memory package using TSV

    -2008 TSV for CMOS image sensors mass production

    - 2008 memory + logic on silicon interposer – start development

    -2010 announce DRAM stacked memory with TSV commercialization

    (all of these can be found in past editions of PFTLE and IFTLE)

    Cho indicated that mobile products will require more than 25 GB/sec bandwidth in ~ 2012 and therefore “..wide I/O memory with TSV is the only solution” There will be two platforms for the systems LSI group: Interposer and memory on logic as shown below.
    They are developing 6 x 50 copper TSV middle technology with O3 TEOS liner . Their process flow is shown below:
    During process development they have dealt with the following challenges:

    - High AR TSV filling
    - Cu extrusion
    - Stress impact on devices
    -Copper contamination (through sidewall and during backside processing)

    By eliminating voids during the plated copper filling they were able to achieve 99.57% via chain yield.

    Cho lists (3) ways to deal with Cu extrusion:

    - Tungsten TSV
    - Cu TSV last backside
    - Via size and depth reduction

    They have determined a workable depth vs diameter space using the 3rd option which results in less than 0.2 um extrusion. [ recall this was first shared with us by Bob Patti – see PFTLE 53, “You Can’t Always Get What You Want”]

    They worry about copper contamination when backside processing due to a decrease in the gettering layer (see previous discussions in PFTLE 117, “On copper diffusion, gettering and the denuded zone”]

    Cho indicates that they will not use W because of the severe wafer bow that even 1 um of W imparts to a 300 mm wafer. They also see severe Si cracking and IMD cracking due to the high W stress.
    Cho expects to see mass production from his side of the business in 2013.

    Eric Beyne - IMEC

    Conference co-chair Eric Beyne, program director for advanced packaging and interconnect at IMEC . The IMEC standard processes have been discussed several times previously [ see PFTLE 122, “3-D IC at the IEEE ISSCC” ; PFTLE 93, “ Semicon TechXPOTs” ]

    Beyne indicates that high speed graphics applications are demanding 512 GB/sec memory bandwidth and thus agrees with the consensus that 3D with TSV is the only way to go.

    The POR for their 3D TSV middle process (3D-SIC) is 5 x 50 um which looks like it is becoming an industry standard.

    Their wafer thinning technology achieves a less than 1.6 um TTV for a 300 mm wafer thinned to 50 um.
    Their Cu/Sn micro bump bonding technology is currently at 25 um bumps on 40 um pitch.
    Jean-Marc Yannou – Yole Developpment

    Yannou focused on the use of 3D interposers for 2.5D technology and offered the following proposed interconnect gap timeline showing that silicon / glass interposers offer 10x more resolution and finer pitches than traditional organic substrates.

    Yole reports that they have found 8 categories of applications for silicon / glass interposers as shown below:

    Arif Rahman – Xilinx

    Arif Rahman, principle engineer at Xilinx gave further details on their next generation FPGA choices that have been reported recently [ see IFTLE 23 , “Xilinx 28 nm Multidie FPGA?”]

    When asked about their choice of a silicon interposer for their next generation FPGA, Arif Rahman commented that “ it appeared to be the most manufacturable way to offer product performance during our required timeline” which I interpret as “”full 3D is not quite to the point that we were ready to bet the farm on it”

    The interconnect on the interposer is done at 65 nm technology. In terms of scalability Rahman noted that the technology was currently limited by “?how big an interposer you can get”

    Note: After the conference Arif left word that he had moved to Altera - interesting !

    Larry Smith - Sematech

    In their 3D program update, Smith indicated that after much study and consultation with its members, Sematech was focused on 5 x 50 um copper vias middle with AR = 4-10 and pitch of 10-50 um. Their status assessment is shown below:

    Paul Enquist - Ziptronix
    Ziptronix highlighted their program with Kodak which produced a 1.5 MPixel BSI (back side imaging) CMOS Image sensor with 1.25 um pixel pitch as shown below.
    NOTE: For those not paying attention, ZIptronix has filed patent infringement charges against TSMC and Omnivision [see "Ziptronix accuses Omnivision, TSMC of patent infringement"
    Lisa McIlrath – R3Logic

    Lisa McIlrath, CEO of R3Logic was one of the first to understand and tackle the EDA requirements of 3D IC technology. [ see PFTLE 102, “The Four Horseman of 3D IC” ]

    She had what was probably the quote of the conference when she astutely stated “3D Integration will become mainstream when it is the best economic alternative” Simple yet accurate ! From her design perspective she feels that this will occur by maximizing IP re-use.

    Philippe Royannez - IME

    IME 3D technology has been discussed previously [see PFTLE 98, “ TSMC Confirms 3D Intent / Singapore Launches 3D IC Consortium “ ]

    Philippe Royannez, Director Sytem & Digital IC at A-STAR updated activities at IME in Singapore. Royannez indicates that their 300 mm line will be fully operational n the 2nd- 3rd quarter of 2011.

    In keeping with the cost reduction theme, Royannez indicated that IME “ has solutions to most of the technical challenges now. The real focus now needs to be making these solutions low cost. “

    When it comes to EDA Royannez notes that “designers understand the theoretical benefits of TSV but cannot quantify it precisely and don’t quite understand what to do to use them” He notes that 3D IC EDA flow “is more evolution than revolution?all the ingredients are there” but then quickly added “..for true 3D IC, that is the spreading of blocks across layers, certainly we’re not quite there yet, but for initial 3D programs we are in pretty good shape”

    In an interesting blood pressure monitor application Royannez made the point that we need to be focused on system level integration. In this application shrinking the size of the circuits and making them faster will not have any impact on the size of the battery which will continue to drive the overall size of the device.

    Tzu Kun Ku - ITRI

    The ITRI Ad-STAC ( Adv Stacked system Technology and Applications) program has been detailed previously [see PFTLE 105 “Taiwanese Focus on 3D IC”]

    The ITRI 3D program currently covers both chip stacking with TSV and the use of 3D interposers. There are currently 120 technologists assigned to their program (80 design, 40 process development). Their TSV formation roadmap is shown below. Their 300 mm line is in place and their baseline process is scheduled to be completed end of this year.

    Of interest is their slide on the benefits of interposers shown below:

    For all the latest in 3D IC and advanced packaging stay linked to IFTLE, Insights From the Leading Edge?




    IFTLE 35 3D Highlights at the RTI 3D ASIP Part 1

    January 29, 2011 11:48 AM by Garrou
    This week we begin a look at activities at the RTI 3-D Architectures for Semiconductor Integration and Packaging Conference ( 3d ASIP) held in Dec 2010 in Burlingame CA . This is the longest running 3D conference (since 2003) and is focused on both technical developments and the commercial infrastructure. Once again an excellent group of commercial technologists and business people were assembled to share their views on the commercialization of this technology.

    Lets first take a look at the Keynote presentations:

    Keynote Speakers: Subramian Iyer (IBM), Douglas Yu (TSMC), Yi-Shao Lai (ASE) and Antun Domic (Synopsys)

    Subramanian Iyer, IBM

    Confirming what PFTLE and IFTLE readers have been reading for several years now Iyer points out that :

    - Scaling, strain engineering, and improved materials (eg. Hi K) will continue to improve performance , though at diminishing rates and certainly with diminishing returns

    - A combination of voltage supply reduction, power budget constraints and design IP migration suggest that the days of dramatic raw performance gains are over

    - Performance must come from elsewhere - Low latency memory integration provides significant system leverage

    Iyer commented that he had spent the last 10 years of his life “..trying to get more memory closer to the processor”. Iyer indicated that integrating large amounts of low latency memory is one of the biggest challenges for modern multi-core processor design. Since modern processors contain 60-70% embedded memory, taking that memory off chip and using TSV to make such memory low latency and high bandwidth can in fact cut the size of the processor chip by as much as 50%. In addition placement of thin film deep trench decoupling caps can give a 5-10% performance improvement by stabilizing the power distribution.

    Iyer labeled TSV as “..a necessary evil” which “..mess up logic or memory designs”. He adds that the TSV designs need to be done efficiently and adds that “ we can do this with about a 5% penalty on the DRAM”

    Iyer gave us indications for the first time that all vias middle are not equal. In fact he suggested that for some circuits intercepting at layer 4 might be the best circuit option. “..integration into oxide vs low K levels can be advantageous since they are much stronger and able to withstand the stresses that the TSVs generate on the structure” Iyer adds that one is “.. always trading off integration difficulty vs lower wirability capability due to blockage of the interconnect layers by the TSV.

    Douglas Yu – TSMC

    Dr. Yu, Sr Director of the Interconnect and Packaging Division, focused his presentation on the overall issues of packaging advanced node chips and how that relates to the future requirements for TSV and 3D stacking.

    Yu indicates that with the rapid cost increases imposed by scaling TSMC sees chip scaling migrating into “system scaling” and 3D technology as being part of that whole movement.

    Yu sees copper TSV and vias middle becoming the industry standards (as IFTLE has predicted for many years now) and he sees the copper protrusion issue as being solved [ see IFTLE 34 “3D IC at the 2010  IEDM” and “Cu protrusion, keep-out zones highlight 3D talks at IEDM” for details ]. They are currently comfortable with 50 um wafer thickness although they expect to go lower.

    When asked about their commercial commitment to silicon interposers Yu responded “ Yes we will offer commercial silicon interposers as we have recently announced with our customer [Xilinx]" [ see IFTLE 23, “Xilinx 28 nm Multidie FPGA?”]

    Yi-Shao Lai – ASE

    Dr Lai filled in for Ho Ming Tong , who we were told was called away for an internal corporate meeting involving “a big investment for 3D IC”. Later in the day we heard from ASE that the budgeting was approved.

    Lai indicated that ASE felt the industry was in much better shape for 3D IC then it was 3 years ago when ASE began looking at this technology in earnest.

    Echoing the feeling of many participants Lai commented that the infrastructure could only be built by everyone “?sharing critical information without leaking proprietary know how” Lai also requested further standardization of the supply chain. “ ..if chips will come from 3 or 4 foundries and the OSATS are chosen to do the backside processing and stacking, must the incoming materials be standardized so that OSATS can have a standard process for minimized cost? “

    Anton Domic - Synopsys

    Anton Domic, Sr VP and GM at Synopsys tried to give the EDA perspective on the migration from 2D to 3D. The theme for Synopsys, a late entrant into the 3D arena was that 3D was “heating up”.

    Much is being made in other blogs about the comparison Domic made about 3D integration CoO. He indicated that 3D IC had a 5% impact on 300 mm wafer production and compared that to SOI (5%) and high k gates (10-20%). My feeling is that this was a generic statement and was made to indicate a relative comparison to things people all readily accept are happening.

    We all understand that 3D is not a unit operation, it is an approach, and as such there is not one number to indicate its impact on cost. Cost modeling for 3D technology must be made on a system basis and as such there are NO numbers out there that I can say I believe yet. Now that real 3D IC technology (TSV, thinning, stacking) has been announced for memory [ see IFTLE 8, “3D Infrastructure Announcements and Rumors” ; IFTLE 27, “Era of 3D IC Has Arrived with Samsung Commercial Announcement” ] we will really begin to understand the true cost of implementing these technologies.

    The same is true for and for 2.5D silicon interposers [ see IFTLE 23, “Xilinx 28 nm Multidie FPGA?”; IFTLE 27, “Era of 3D IC Has Arrived with Samsung Commercial Announcement” ]

    Domic reiterated the point made by IBM’s Iyer – that TSVs are HUGE and added that TSV number and placement is crucial, mobility changes due to SPE (stress proximity effects) can be significant and thus keep out zones can be significant and that test is challenging.

    When discussing silicon interposers which Domic labels “there already” because of the Xilinx announcement, Synopsys offers the following Implementation flow:

    Tezzaron continues their scaleup with Chartered (now Globalfoundries) and claims their available capacity is about 40K wafers/mo . Tezzaron is currently fabbing ca. 100-125 200 mm wafers / mo according to our friend Bob Patti.

    ?Next week we will continue our look at 3D activities at the 2010 RTI 3D ASIP?

    For all the latest on 3D IC and advanced packaging stay linked to Insights From the Leading Edge?..

    IFTLE 34 3D IC at the 2010 IEDM

    January 22, 2011 12:14 PM by Garrou
    With the general belief that CMOS is becoming economically if not technically less and less viable as the industry continues to scale, it is to be expected that we will be seeing more and more 3D IC presentations at the IEEEs premier IC conferences namely the ISSCC (Int Solid State Circuits Conference) and the IEDM (Int Electronic Device Meeting).
    At the 2009 IEDM TSMC researchers called 3D IC “an enabling foundry technology for 28 nm and beyond” after they studied the impact of 3D thinning ( to ~ 50 ?m) and fine pitch bonding on strained and unstrained 40 nm Cu / ELK CMOS and Koyanagi and co-workers from Tohoku University examined the electrical implications of mechanical stress / strain and metal contamination on thinned 3D LSI.[ see PFTLE 117, “ On Copper Diffusion, Gettering and the Denuded Zone “. In 2010 3DIC became even more prominent at the IEDM.

    During his 2010 keynote presentation Jim Clifford, Sr VP and Operations GM indicated that scaling could get to expensive and therefore Qualcomm was backing 3D TSV technology and urged the rest of the industry to collaborate on 3D IC and invest in its infant infrastructure.


    Dr Kinam Kim, President of Samsung Advanced Institute of Technology (SAIT) in his keynote presentation on the future of silicon technology noted that conventional scaling was becoming more challenging in terms of materials, patterning and electrical performance, and now requires huge capital investments. He commented that current scaling strategy “?is almost unusable for the 10 nm node?”.

    Samsung sees mobile processors, FPGA, and high performance ASIC applications will require “ more functionality at greater speeds” which will require “... a heterogeneous device stack with a wide I/O interface and high data rates”. Kim notes that “..the semiconductor industry is adopting 3D IC technology as a promising solution for these devices”. Kim added that short term TSV based IC technologies along with 3D Si interposers will accelerate the adoption of 3D system-in-package (SiP) heterogeneous integration. “..This might be the next driver for genuine 3D IC devices in the future with tremendous benefits in footprint, performance, functionality, data bandwidth, and power”


    In their presentation on 3D integration for the 28 node and beyond, TSMC indicates that “optimized fabrication processes and materials selection are critical to achieve high device performance, yield and reliability for 3D technology integration on 300 mm wafers” . They claim to have successfully integrated 3D technology into advanced CMOS foundry processes which is “.. a major step toward 3D production”.

    Of interest are the TSMC studies on Cu protrusion and its effects on device fabrication and reliability. They find that the amount and shape of protrusions, (shown in the figure below) depend on several process parameters, including the electroplating processes (ECP), electrolyte selection, impurities co-deposited with Cu, Cu grain size distribution, and post deposition annealing conditions. As the system cools down from thermal excursions, mismatches in CTE between silicon, oxide liner, and Cu fill introduces two un-desirable effects. The first effect is Cu extrusion around the center of the TSV, shown below. The second effect is liner cracking. Having the smallest CTE, the oxide liner undergoes high stresses exerted by the Cu TSV and the Si substrate. The maximum stress concentration is found to be near TSV bottom, where the majority of liner cracks were observed that causes significant current leakage.

    It is also shown that residual stress remains in Si substrate after TSV processing. For devices using strain-Si technology, an active device a keep-out zone surrounding each TSV is required to minimize TSV impact on performance.

    ?IBM / NCTU

    In a joint program between IBM Yorktown and National Chiao Tung Univ (NCTU) in Taiwan “oxide recessed” vs “lock & key” bonding structures were compared and contrasted.
    For the lock-n-key structure, the “lock” part is achieved by recessing Cu, while the “key” part is fabricated with recessing oxide. The recessed amounts of both parts are carefully fabricated to make sure two Cu surfaces can contact during bonding. In addition, the lock-n-key structure allows oxides from both wafers to simultaneously bonded during Cu bonding (Cu-oxide hybrid bonding).

    After alignment, wafers were bonded at 400°C for 1 hour under a 10,000 N force in the ambient of 2x10-4 torr. The bonded wafers were then diced and held at 200°C for 70 hr in air to test for corrosion. The lock-n-key structures show clear well-bonded structure, indicating excellent corrosion resistance whereas the Cu bonded, oxide-recessed structures have become significantly corroded. In addition, the bond strengths of lock-n-key structures are higher than those of oxide-recessed ones.


    3D induced stresses are one of the key constraints in a 3D design flow that must be controlled in order to preserve the integrity of front end devices. IMEC and some of their consortium members (Panasonic, Qualcomm, Samsung) examined the stress induced by single- and arrayed TSVs, quantifying the stress distribution and determining its impact on both analog and digital FEOL devices and circuits. Stress aware design and the right definition of keep out zone will be needed to optimize silicon area.

    From stress modeling studies such and experimental data points, transistor “keep out zones” are derived for both digital and analog circuits. The IMEC researchers conclude that the KOZ for a large matrix of TSVs is over 200 µm for analog circuits and 20 µm for digital circuits and add that the complex interaction of stress components makes it difficult to use simple design rules without sacrificing large layout area. Depending on the TSV footprint and the number of TSV required different TSV placements will be optimum (single, row, matrix).

    Tohoku Univ

    Mechanical stress / strain in thin 3D structures was once again the topic of study for 3D technology veteran Professor Matsui Koyanagi of Tohoku University. The Tohoku group has concluded that high performance 3D-LSI require 104 to 105 micro-bumps/TSVs and a die thickness of ~ 20 ?m. They find that mechanical strain/stress and crystal defects are produced in extremely thin of 3D-LSI wafers (~10 ?m) not only during wafer thinning, but also after wafer bonding using fine-pitch, high-density microbumps and underfill curing. Cu/Sn microbumps induce stress/ strain at Si wafer surface, which penetrates deeper for larger bump size and wider for smaller bump pitch. They note that this locally induced stress / strain can result in a 10% change in the ON current of p-MOS transistor.

    Koyanagi also reported that the metal of the TSV and microbumps not only induce stress / strain (due to the difference in the CTE between Si and metal in thinned Si substrate but also can be the cause of metallic contamination.

    For all the latest on 3D integration and advanced packaging stay linked to IFTLE?

    IFTLE 33 Micron 3D Response, Sematech Standards, Leti 300 mm Line

    January 18, 2011 5:50 PM by Garrou
    Since the fall is always an busy time for professional meetings around the world, and nearly all microelectronic meetings are trying to give you 3D IC coverage, I’m having a tough time covering all of this information in a timely, chronological way. The major items are hitting SST as articles but the more data driven information will simply have to work its way through the que. This week an extra blog dedicated to recent 3D IC news items of interest.

    With the recent Samsung announcement of stacked 3D memory products [ see IFTLE 27, “Era of 3DIC Has Arrived with Samsung Commercial Announcement”] IFTLE predicted a response from the other memory suppliers and actually asked “ Will Hynix or Micron announce next ?”

    Well the answer is in and it is Micron !

    Mark LaPedus at EE Times reports that Mark Durcan, COO of Micron, at the recent IEEE ISS meeting in Half Moon Bay, commented that Micron is ''sampling products based on TSVs” and that “..mass production for TSV-based 3-D chips are slated for the next year or 18 months'' and that “ Elpida, Samsung, and Toshiba are also in various stages of devising TSV-based 3-D chips” [link]


    Andy Rudack at Sematech updates us on the 3D IC committees put in place by the Semi / SEMATECH alliance.
    CEA Leti Dedicates 300 mm 3D IC Line

    CEA-Leti (the Laboratory for Electronics and Information Technology), a long time player and recognized leader in 3D IC technology development, dedicated its 3D-integration 300mm lines this week. CEA-Leti operates 8,000-m² state-of-the-art clean rooms, on 24/7 mode, on 200mm and 300mm wafer standards.

    By adding this technology to its existing 300mm CMOS R and D line, Leti now offers thecomplete package of chip design, fabrication and 3D stacking and packaging on both 200mm and 300mm wafers.

    The new line will allow prototyping capabilities in alignment, bonding, thinning, and interconnects in specific integration schemes for optimized die stacks and building efficient advanced-systems solutions at 300 mm.

    For all the latest in 3D IC and Advanced packaging technology news, stay linked to IFTLE??

    IFTLE 32 3DIC in Munich part 2

    January 14, 2011 9:44 AM by Garrou
    Continuing our look at presentations from the IEEE 3DIC Conference held in November 2010 in Munich.

    IBM – 3D From a Server Perspective

    Jeff Burns, IBM Dir of VLSI systems at Yorktown Heights, offered the perspective that 3D technology will require many changes to architecture, VLSI design, design IP, tools, technology, and manufacturing. In total this will be much larger in scope than a CMOS technology generation, rather it will be similar to the transition from bipolar to CMOS.

    Burns offered the following considerations for 3D chip design:
    Soitec / CEA Leti - Cu-Cu Direct Bonding

    We have had extensive discussions on Cu-Cu direct bonding in the past [ see PFTLE 58, “Fisk, Buckner and Pasta on the North End”; PFTLE 26, “3D Practitioners Assemble at Ft McDowell”; IFTLE 6, "Copper-Copper and IMC Bonding Studies at 2010 ECTC” ]

    We have also noted that Soitec has arrangements in place to scale up and offer for license CEA Leti technology in this area [ see PFTLE 89, “The French Connection”] .

    At the 2010 IEEE 3DIC in Munich Soitec presented more details on this process. Direct bonding, unlike thermo compression or eutectic bonding, is performed at room temperature under atmospheric pressure and is based on molecular adhesion between surfaces in contact. Cu-Cu direct bonding requires flat surfaces with surface micro roughness of both Cu and oxide materials of less than 1 nm for successful bonding. Soitec indicates that standard damascene copper CMP does not provide the desired surface topography needed for a successful bonding process due to Cu pad dishing and oxide erosion. An optimized CMP process has been developed to limit the surface topography between the copper pads and the surrounding oxide dielectric. The special CMP surface preparation step leads to very smooth surfaces, the micro-roughness of both Cu and dielectric surfaces beings as low as 4-5Å. In addition the CMP renders the surfaces highly hydrophilic with the contact angle below 5°. The figure below shows that the planarization steps a) and b) are common steps in damascene BEOL while the step c) represents a specific step required for Cu-Cu direct bonding.

    The figure below shows the cross section TEM images taken right after bonding (a)no annealing and after successive annealing steps at (b) 200°C, (c) 300°C and (d) 400°C during 30 minutes. Cu interdiffusion is apparent in the 200°C annealed samples, Cu grains being formed between the two layers. At higher temperatures, growth of copper grains is observed across the bonding interface.
    In case of patterned Cu/oxide surfaces, oxide-oxide, Cu-Cu and Cu-oxide interfaces are formed during bonding. The bonding strength of the interfaces is shown in the figure below. The highest bonding energy is obtained for Cu-Cu interfaces, followed by SiO2-SiO2.
    ?Bonding of 5?m Cu pads has been successfully performed with a corresponding bonding energy of more than 1J/m2 obtained upon 200°C post bond anneal. The bonding strength achieved has been sufficient to sustain post - processes such as silicon back thinning using coarse and fine grinding. Using a 5mm edge grind process, the backside thinning down to 5?m thin silicon substrate was realize with no delamination of the bond interface. Since no external force or pressure and temperature cycle is applied during bonding process, excellent alignment with minimum mechanical deformation is obtained.

    Kansai Univ - “All Wet” Fabrication Technology

    Some readers have pointed out that it has been several months since I gave a lesson on American idioms ( phrases which do not mean what the sum of the individual words mean). Certainly this Kansai Univ paper gives me the opportunity to do that.

    As many of you know Alchimer has been reporting for several years on their “wet process” for insulation, barrier and seed [ see IFTLE 11, “In and Around the Moscone part 2”].

    I have teased them in the past saying that I would indicate that their process was the only “all wet” process available. In general English usage in the US “all wet” means “completely wrong”. Searching for the original meaning of this idiom reveals it has been in use since the 1920’s although the origin of the meaning is unclear. I am sure the Kansai researchers are not meaning to describe their “fully wet” fabrication process as “completely wrong”.

    The Kansai process uses electroless deposition of thin barrier layers of NiB and CoB catalyzed by the use of nano particles catalysts (Au, Pd, Pt) which are adsorbed on the SiO2 insulation of the TSV sidewalls that have been treated with 3-APS (3-aminopropyl-triethoxysilane coupling agent). A conformal electroless Cu layer can then be deposited on the barrier layer without catalyst by displacement plating.

    Copper migration through the CoB and NiB barrier layers were examined by resistivity changes upon annealing. Cu / NiB was found to be stable up to 300 C and Cu / CoB up to 400 C.

    Now, the community appears to have two options for a “fully wet” barrier and seed process.

    ASET – 3D Architecture for Processor – Memory Integration

    Ito of ASET described two 3D interconnection architectures (block and sandwich stacking) for stacked processor-memory LSIs. In the sandwich configuration, memory chips and processor chips are stacked alternately, and vertical interconnects in each PU-CHIP are divided into two groups: interconnects

    for global communications and interconnects for local 3Dmemory communications. Compared with block stacking configuration, sandwich stacking architecture shows 38% fewer vertical interconnects for the same throughput and reduces power consumption by 21%.
    The performances of three-dimensional stacking chips with 64- processor cores were also estimated. 3D in sandwich stacking architecture achieves twenty-times-lower power consumption of inter-chip communications than conventional 2D integration.

    ASET – Copper / Polymer Hybrid Bonding

    In another ASET presentation Aoki of ASET detailed their studies on copper / polymer hybrid bonding technology. We have seen copper / polymer bonding previously from both IMEC [ see PFTLE 10, “3D IC at the 2010 IEEE IITC” ].

    For such bonding technology the surfaces of the metal and polymer must be globally flat. ASET applied a single damascene process for forming the hybrid bonding surface. To reduce surface-step height caused by copper dishing, a technology to co-planarize both the copper and polymer was developed. Polybenzoxazole (PBO) was used as the polymer for sealing bumps because it features positive-tone photosensitivity, high chemical resistance, and high thermal stability.

    PBO polishing rate can be controlled by optimizing the PBO cure temperature. From the figure below you can see that curing the PBO at approx.. 280 C results in a very small step height ( less than 50 nm) which allows a globally planarized 200 mm wafer to be obtained.
    For all the latest in 3D IC and advanced packaging stay linked to IFTLE, Insights From the Leading Edge???


    IFTLE 31 Oxide Bonding Patent Litigation Has Begun

    January 8, 2011 11:29 AM by Garrou
    As has been expressed on IFTLE many times, full 3D IC requires: TSV, thinning and bonding. As of yet there is no real clarity as to who “owns” any of these technology although there have been many boisterous claims out there being made.

    In 2006 while the industry was deep in the R and D phase of 3D IC technology, I wrote a piece concerning “posturing and positioning” as the first phase of 3D IC technology commercialization [ “Posturing and Positioning in 3-D IC’s”, Semiconductor Int. April 2007]. The premise was that the 3D IC announcements at the time by Intel, IBM, Samsung, NEC, Elpida were the beginning of commercialization, stage (1) or “the bragging stage” if you will, where technology companies like peacocks strut around showing their feathers and announcing “we are the best”.

    Stage (2) “real commercialization” came in 2010 when Elpida/UMC [see IFTLE 8, “3D Announcements and Rumors”]and Samsung [see IFTLE 27, “The Era of 3D IC Has Arrived with Samsung Commercial Announcement” ] announced 3D IC based memory products (albeit for late 2011- 2012). The expectation is that this will cause further announcements from competitor companies attempting to keep up in the technology race , a pattern we saw recently in the introduction of TSV technology for CMOS image sensors [see PFTLE 46,“.....on Mechanical Bulls, Rollercoasters and CIS with TSV” ].

    Stage (3) I would define as the period where standardization begins to occur, the infrastructure begins to “gel” and technology ownership begins to clarify. For multilayered, complex technologies like 3D IC technology ownership is usually determined in the courts. Dec 6th 2010 is the date that initiated the technology ownership determination for “oxide bonding” technology. This is when Ziptronix filed a complaint against TSMC and Omnivision in Federal Court alleging “willful and deliberate” infringement of several patents [ USP’s: 7,387,944; 7,335,572; 7,553,744; 7,037,755; 6,864,585; 7,807,549; ] owned by Ziptronix pertaining to low temperature oxide bonding. The original SST article can be found here [link]. In question here is the use of oxide bonding for backside illumination in CMOS image sensors [see PFTLE 40, “Backside Illumination (BSI) Architecture next for Next Generation CMOS Image Sensors”]

    Most of the CIS manufacturers have moved to BIS technology per a recent market study by Yole Developpment [ see “ CMOS Image Sensors Technologies and Markets -2010”].

    Instead of illuminating a CMOS image sensor from the top side (front) of the die, backside illumination (BSI) collects photons from the backside so the light enters the device unobstructed by the metal and dielectric layers of the interconnect structure as shown in the figure.

    ?According to Yole, CMOS BSI sensor technology is being used by Sony and has been announced in video camcorders and digital still camera products by Casio, Nikon, Ricoh, Samsung, JVC and Fujifilm.

    Cell phone camera image sensor suppliers Omnivision, Aptina Imaging, Toshiba, Samsung and STMicro also appear ready for BSI products to appear in early 2011. Yole expects BSI technology to be responsible for a little over $1B (~17% of CIS sales) in 2012.

    TSMC has presented their latest BSI technology in the paper "A Leading-Edge 0.9?m Pixel CMOS Image Sensor Technology with Backside Illumination:Future Challenges for Pixel Scaling" at the 2010 IEDM. They describe the "device wafer runs through a planarization process and is bonded with a carrier wafer. The bonded wafer is then mechanically and chemically thinned down from the bottom side of the device wafer to the target thickness". The process in question is the wafer bonding process. The qustion raised by this complaint centers around whether the accused are using oxide wafer bonding for their OmniBSI® technology, if so, whether the the oxide surfaces are treated with plasma or other chemicals and whether the Ziptronix claims in their numerous patents on the topic are indeed valid. TSMC and its subsidaries Xintec and VisEra appear ready to deliver CMOS image sensor devices to Omnivision.

    Chipworks has done reverse engineering on Omnivision products such as the OmniVision OV5642 1.4 ?m, back side illuminated (BSI) 5 Mp CIS [link] and teardowns of communication devices such as the HTC EVO 4G Smart Phone which they found contained the OmniVision OV8812 8 Mp Image Sensor chip (below).
    BSI technology requires a solution for handling thinned wafers. A typical solution is to direct oxide bond the sensor wafer front surface to another oxide coated wafer which can then serve as a permanent “handle wafer” for the thinning operation.

    Direct oxide bonding processes require extremely smooth (0.5 nm RMS) and clean surfaces which are readily achieved with standard CMP. When such SiO2 surfaces are placed into contact, they initially form relatively weak “van-der-Waals” bonds. Subsequent heating to elevated temperatures is necessary to achieve high bond strength through the formation of covalent Si-O-Si bonds. The high thermal budget required for this condensation reaction to proceed ( typically greater than 800 C) is not suitable for most devices, however, modifying the surface chemistry allows the formation of chemical bonds at significantly lower temperatures.

    Recent reports from EVG indicate that oxide bonding currently has 35% better placement accuracy and better throughput than polymer bonding as shown in Table [ see PFTLE 41, “3D Integration Stays HOT at Semicon West”]

    Using oxide bonding for the “back-end, bonding to carrier step” would result in low temp, high throughput bonding would result in excellent CTE match and positional accuracy.

    Ziptronix technology for BSI is centered around ZiBond? which they claim allows one to achieve significantly higher bond energy between wafers after treatment with various surface “activating and terminating” processes. The direct oxide bonding, which is initiated at low temperature, is characterized by a very high bond energy between the surfaces. One example of Zibond? simply requires a plasma treatment followed by an aqueous ammonium hydroxide rinse. By such surface treatments bond energies in excess of 1 J/m2 are reported.

    ?In 2008 Donabedian was quoted as saying that “the broad and fundamental nature of our patent portfolio, leads us to believe that any use of a oxide low temperature bonding process is highly likely to be covered by one or more of our patents” [“3D Startup Proves Ahead of Its Time”, Semiconductor International, Oct. 2008]. Donabedian further stated that “...while there are commercial tools in the market that claim to support low temperature oxide bonding processes, Ziptronix has not granted, nor does it intend to grant any licenses under it’s IP to the manufacturers of this equipment...anyone running a low temperature oxide bonding process as part of their manufacturing scheme is likely to be infringing on our IP” [“Ziptronix Pioneering 3D Integrated Circuit Process Technology”, i-Micronews, Aug. 2008]. Was this bravado or simply a statement of fact ? We will soon see !

    Next week we will continue our look at presentations from the IEEE 3DIC in Munich.

    For all the latest on 3D IC technology and advanced packaging stay linked to IFTLE????????..

    IFTLE 30 2010 IEEE 3DIC in Munich

    January 1, 2011 2:25 PM by Garrou
    In its new incarnation [see PFTLE 100, “3D IC in the City by the Bay” for historical perspective ] the IEEE 3DIC Conference met in Munich under the leadership of European co-chairs Peter Ramm (Fraunhofer EMFT Munich) and Eric Beyne (IMEC). Next years meeting (fall of 2011) will be held in Tokyo with Prof. Mitsumasa Koyanagi (Tohoku Univ) and Mr Morihiro Kada (ASET) as leaders. Below is a photo of this years session chairs and speakers “bookended” by chairman Peter Ramm on the left and old friend Fred Roozeboom on the right.
    First we will take a look at cost modeling 3D processes and interposer technology and in hte next blog we will look at some other interesting presentations.

    IMEC cost modeling

    We would certainly all agree that the many reported manufacturing options for 3D integration could have a different impact on the cost of a 3D-stacked system. IMEC has developed a cost model to compare the costs of different process flows. The model revels a slightly lower processing cost for TSV middle (3D-SIC; 5 x 50 um) vs TSV backside (3D-WLP; 35 x 50 um); backside wafer preparation for Cu-Cu bonding and W2W Cu/Sn bonding as shown below.

    Of great interest to IFTLE is the IMEC plot of processing cost (etch, liner, barrier, plate) vs TSV depth. Increasing the TSV depth at a given diameter (i.e increasing the AR while holding the diameter constant) affects etching, liner and barrier and plating negatively. In the chart shown below, one can see that SIC and WLP cross over at about 75 um. The model predicts a 40+% increase in cost to make a 5 x 100 3D-SIC TSV than a similar 5 x 50 TSV. Similar conclusions have been reached by EMC-3D [ see PFTLE 68 “Like Swallows Returning to San Juan Capistrano” ].

    The model also concludes that the anticipated lower stacking yield of a W2W stacking strategy results in a higher cost for both the 3D-SIC and the 3D-WLP process flows.

    Silicon Interposers

    Papers from Fraunhofer IZM – EMFT Munich and RTI Int addressed fabrication aspects of 3D IC Interposers.

    Weiland at IZM Munich described a 400 mm sq x 100 um thick interposer with 20 um dia TSV (5:1 AR) on 50 um pitch. The sidewall insulation consisted of thermal oxide followed by O3/TEOS SACVD (sub atmospheric CVD) and the barrier layer was TiW. The 3 layer RDL, built on the TSV is based on photo polymer (not identified) and plated copper. Wafer thinning to 100 um was done with a carrier wafer and temporary adhesive (stable to 150 ?C to allow backside deposition of low temp CVD SiO2.

    ?Malta of RTI Int examined the fabrication of interposers by TSV first and TSV last processes. In the RTI backside TSV last process TSVs are formed after the front-side thin film processing is completed. It is not necessary to fill the TSVs since dry film resist can be used for patterning of back-side metal after the TSVs are formed. Since the vias do not need to be filled, TSV reliability concerns due to Cu-Si CTE mismatch are also reduced. One of the primary advantages of this approach is that the critical thin film processing is done on a blank Si wafer, with no limitations imposed by Cu-metallized TSVs. However, the TSV processes must be compatible with the thermal limitations of the front-side thin film layers which may include PECVD-TEOS or polymer dielectrics.

    The biggest challenge occurs in making the interconnections between the TSVs and the front-side metal during “bottom clear” etch which selectively removes the insulator from the base of the TSV, exposing the metal, while not etching the sidewall isolation. Too much etching can result in high TSV leakage currents, due to sidewall passivation loss, while too little etching can result in high resistance interfaces.

    In the TSV first process the TSV are etched as blind vias, from the front surface of the wafer. They are then passivated, coated with seed metal, and plated with Cu and the Cu overburden on the front-side is removed by CMP. The wafers are then thinned using backgrinding and back-side CMP, until the TSVs are exposed. After repassivation of the back-side, the interposers undergo front side thin film processing and backside metallization. A significant advantage is that the passivation “bottom clear” etch is not required, as in the TSV last approach. Also, since there are not other materials on the wafer at the time the TSV are insulated and filled, high temp processes such as thermal oxidation can be used to produce high quality oxide insulation. There is concern over the copper filled TSV CTE mismatch issues. Malta suggests that a way to address these reliability concerns is to “?limit their diameter” but adds that “In order to have small diameter TSVs with an acceptable aspect ratio for processing, it may be ecessary to thin the wafer significantly. Most likely, freestanding wafers can only be thinned to a few hundred microns. Below that, the use of carrier wafers would be required not only for the thinning, but for any subsequent processing which remained” Current studies were done with 100 um dia TSV with 6:1 AR. TSV passivation was 2 um thermal oxide.

    Back-side passivation tests was examined with photo BCB and PI. Malta did observe thermo mechanical issues during the curing processes at temperatures of 250ºC and 350ºC respectively. Distortion of the dielectric layers was observed in the areas over the Cu-filled TSVs, along with delamination and cracking of the films. RTI believes this is due to an protrusion of the Cu in the TSVs during the dielectric cure. Anneal tests at 400ºC for 1 hour in N2 indicated that the Cu in the TSV went through a permanent expansion of 1.5-2?m during the 400 C exposure as shown below.

    For all the latest in 3D IC and advanced packaging stay linked to IFTLE, Insights From the Leading Edge?.