Ed's Threads

Monthly Archives: November 2015

MPU Cores and Legal Boors

As reported by The Register, AMD has been sued by a customer who claims that the number of Bulldozer cores in some Opteron and FX microprocessor (MPU) chips are fewer than advertised. The claim is based on the argument that a “real” MPU core has it’s own floating point unit for calculations, and that consumers were misled by product claims. I am not a lawyer (IANAL) and have no connections to either side in this case, but AMD’s website (http://www.amd.com/en-us/products/processors/desktop/fx#) now clearly indicates that cores share a Floating Point (FP) scheduler.

The Figure shows that the confusion is due to the design of the Bulldozer microarchitecture wherein a pair of cores is called a module, and each pair shares a branch prediction engine, an instruction fetch and decode stage, a floating-point math unit, a cache controller, a 64K L1 instruction cache, a microcode ROM, and a 2MB L2 cache. The lawsuit claims, “Because AMD did not convey accurate specifications, tens of thousands of consumers have been misled into buying Bulldozer CPUs that do not conform to what AMD advertised, and cannot perform the way a true eight core CPU would (i.e., perform eight calculations simultaneously).”

This is analogous to someone buying a car with a V8 internal combustion engine, and then suing the manufacturer because there are only 4 fuel injectors and not all cylinders fire simultaneously. The claim that “true” multi-cores must be capable of functioning simultaneously is like claiming that “true” multi-cylinder engines must be capable of all cylinders firing simultaneously. AMD has officially responded with the statement that, “We believe our marketing accurately reflects the capabilities of the Bulldozer architecture which, when implemented in an 8-core AMD FX processor, is capable of running eight instructions concurrently.” There seems to be little legal difference between “simultaneously” and “concurrently” but IANAL.

Sure, there’s a technical difference and likely a slight performance benefit to direct fuel injection into each cylinder, but raw performance is only one aspect of the design trade-offs between performance and cost and reliability. Sharing 1 fuel injector between 2 cylinders often provides an optimum of performance/cost/reliability in internal combustion engines. Sharing 1 FPU between 2 logic cores seemingly provides an optimum of performance/cost/reliability in CPUs.


Thermoplastically Deformable Electronic Circuits

Philips is testing a technology developed by imec and CMST (imec’s associated lab at Ghent University) to create low-cost 3D LED packages. As shown at last month’s International Microelectronics Assembly and Packaging Society (IMAPS 2015) meeting, these thermoplastically deformable electronic circuits are already being integrated by Philips into LED lamp carriers, a downlight luminaire, and a omnidirectional light source.

Miniature dome test vehicle with integrated low power LEDs, (a) circuit before forming, and (b) circuit after vacuum forming using a 40mm half-sphere mold. (Source: imec)

Miniature dome test vehicle with integrated low power LEDs, (a) circuit before forming, and (b) circuit after vacuum forming using a 40mm half-sphere mold. (Source: imec)

The technology is based on meander-shaped interconnects, which are patterned using  standard printed circuit board (PCB) production equipment and then sandwiched between 2D thermoplastic polymer (e.g. polycarbonate) sheets. The Figure shows one example in final form after vacuum thermoforming into a 40mm half-sphere mold.
This is a glorious example of “elegant engineering” where a clever combination of materials and processes has been integrated with highly desirable characteristics:  low tooling cost, low direct material cost, easily scalable from lab to fab, low product weight, and high product resilience. This seems to represent almost a new industrial product category that combines a “package” and a PCB.