Tag Archives: circuit

Mott Memristor Chaos could make Efficient AI

Congratulations to Suhas Kumar, John Paul Strachan, and R. Stanley Williams of Hewlett Packard Labs in Palo Alto for showing not just how to make a Mott memristor, but that you can create controlled chaos with one. “We showed that this type of memristor can generate chaotic and nonchaotic signals,” says Williams, who invented the memristor based on theory by Leon Chua. An analysis of the material science and engineering of titanium sub-oxides as practiced by Williams at HPL for the production of standard memristors can be found in one of my old blog posts (http://www.betasights.net/wordpress/?p=1006).

Cross-section TEM of a Mott memristor composed of 8nm niobium dioxide layer between top layer of titanium nitride and bottom pillar of titanium nitride. (Original Image: Suhas Kumar/Hewlett Packard Labs, color commentary by Ed Korczynski)

Cross-section TEM of a Mott memristor composed of 8nm niobium dioxide layer between top layer of titanium nitride and bottom pillar of titanium nitride. (Original Image: Suhas Kumar/Hewlett Packard Labs, color commentary by Ed Korczynski)

The Figure shows a cross-section of a single Mott memristors formed by the region of the 8nm thin niobium dioxide (NbO2) layer that is between the 70nm diameter titanium-nitride (TiN) pillar functioning as bottom electrode and the blanket TiN layer functioning as top electrode.

Such a device exhibits both current-controlled and temperature-controlled (https://en.wikipedia.org/wiki/Mott_transition) negative differential resistance, and the proper choice of current and temperature can result in what I like to term “repeatable” chaos. It is repeatable in that a state can be controlably placed into or out-of chaos using non-linearities in electrical current-flow and temperature. From the abstract of the original article in Nature:

We incorporate these memristors into a relaxation oscillator and observe a tunable range of periodic and chaotic self-oscillations. We show that the nonlinear current transport coupled with thermal fluctuations at the nanoscale generates chaotic oscillations. Such memristors could be useful in certain types of neural-inspired computation by introducing a pseudo-random signal that prevents global synchronization and could also assist in finding a global minimum during a constrained search.

In a simulated circuit, an array of Mott memristors can be integrated with standard memristors to form a simulated Hopfield network (https://en.wikipedia.org/wiki/Hopfield_network). Hopfield nets seem to be some of the most apt models for human memory, so if we can just wire together a sufficient number of NbO Mott memristors with TiO standard memristors then we might be a step closer to functional AI.

Read the fine coverage at IEEE Spectrum:  https://spectrum.ieee.org/nanoclast/semiconductors/devices/memristordriven-analog-compute-engine-would-use-chaos-to-compute-efficiently

Or the Nature article behind paywall:  https://www.nature.com/nature/journal/v548/n7667/full/nature23307.html

—E.K.

PCM + ReRAM = OUM as XPoint

The good people at TECHINSIGHTS have reverse-engineered an Intel “Optane” SSD to cross-section the XPoint cells within (http://www.eetimes.com/author.asp?section_id=36&doc_id=1331865&), so we have confirmation that the devices use chalcogenide glasses for both the switching layer and the selector diode. That the latter is labeled “OTS” (for Ovonic Threshold Switch) explains the confusion over the last year as to whether this device is a Phase-Change Memory (PCM) or Resistive Random Access Memory (ReRAM)…it seems to be the special variant of ReRAM using PCM material that has been branded Ovonic Unified Memory or “OUM” (https://www.researchgate.net/publication/260107322_Programming_Speed_in_Ovonic_Unified_Memory).

As a reminder, cross-bar ReRAM devices function by voltage-driven pulses creating resistance changes in some material. The cross-bars allow for reading and writing all the bits in a word-string in a manner similar to Flash arrays.

In complete contrast, Phase Change Memory (PCM) cells—as per the name—rely upon the change between crystalline and amorphous material phases to alter resistance. The standard way to change phases is with thermal energy from an integrated set of heater elements. The standard PCM architecture also requires one transistor for each memory cell in a manner similar to DRAM arrays.

Then we have the OUM variant of PCM as previously branded by Energy Conversion Devices (ECD) and affiliated shell-campanies founded by tap-dancer-extraordinaire Stanford Ovshinsky (https://en.wikipedia.org/wiki/Stanford_R._Ovshinsky). So-called “Ovonic” PCM cells see phase-changes driven by voltage pulses without separate heater elements, such that from a circuit architecture perspective they are cross-bar ReRAMs.

Ovshinsky et al. successfully sold this technology to industry many times. In 2000, it was licensed to STMicroelectronics. Also in 2000, it was used to launch Ovonyx with Intel investment (http://www.eetimes.com/document.asp?doc_id=1176621), at which time Intel said the technology would take a long time to commercialize. In 2005 Intel re-invested (http://www.businesswire.com/news/home/20051019005145/en/Ovonyx-Receives-Additional-Investment-Intel-Capital). Finally in 2009, Intel and Numonyx showed a functional 64Mb XPoint test chip at IEDM (http://www.eetimes.com/document.asp?doc_id=1176621).

In 2007, Ovonxyx licensed it to Hynix (http://www.eetimes.com/document.asp?doc_id=1167173), and Qimonda (https://www.design-reuse.com/news/15022/ovonyx-qimonda-sign-technology-licensing-agreement-phase-change-memory.html), and others. All of those license obligations were absorbed by Micron when acquiring Ovonyx (https://seekingalpha.com/article/3774746-micron-tainted-love). ECD is still in bankruptcy (http://www.kccllc.net/ecd/document/list/3153).

So, years of R&D and JVs are behind the XPoint Optane(TM) SSDs. They are cross-bar architecture ReRAM arrays of PCM materials, and had the term not been ruined by 17-years of over-promising and under-delivering they would likely have been called OUM chips. Many others tried and failed, but Intel/Micron finally figured out how to make commercial gigabit-scale cross-bar NVMs using OUM arrays. Now they just have to yield the profits…

—E.K.

CMOS-Photonic Integration Thermally Sensitive

As published in the journal Nature, CMOS transistors have been integrated with optical-resonator circuits using complex on-chip sensors and heaters to maintain temperature to within 1°C. While lacking the laser-source, these otherwise-fully-integrated solutions demonstrate both the capability as well as the limitation of trying to integrate electronics and photonics on a single-chip. The Figure shows a simplified schematic cross-section of the device.

Full chip cross-section (not to scale) from the silicon substrate to the C4 solder balls, showing the structures of electrical transistors, waveguides, and contacted optical devices. The minimum separation between transistors and waveguides is <1 μm, set only by the distance at which evanescent light from the waveguide begins to interact with the structures of the transistor.

Full chip cross-section (not to scale) from the silicon substrate to the C4 solder balls, showing the structures of electrical transistors, waveguides, and contacted optical devices. (Source: Nature)

Lead author Chen Sun—affiliated with UC Berkeley and MIT, as well as with commercial enterprise Ayar Labs, Inc.—developed the thermal tuning circuitry, designed the memory bank, implemented the ‘glue-logic’ between various electronic components, and performed top-level assembly of electronics and photonics. The main limitation is the temperature control, since deviation by more than 1°C results in loss of coupling that otherwise provides for P2M/M2P transceivers:

* Waveguide Loss - 4.3 dB/cm,
* Tx and Rx Data Rate - 2.5 Gb/s,
* Tx Power - 0.02 pJ/bit,
* Rx Power - 0.50 pJ/bit, and
* Ring Tuning Control Power - 0.19 pJ/bit, so
* Total power consumption = 0.71 pJ/bit.

The Register reports that this prototype has a bandwidth density of 300 Gb/s per square millimetre, and needs 1.3W to shift a Tb/s straight from the die to off-chip memory. A single chip integrates >70 million transistors and 850 photonic components to provide microprocessor logic, memory, and interconnect functions.

—E.K.