Tag Archives: device

Mott Memristor Chaos could make Efficient AI

Congratulations to Suhas Kumar, John Paul Strachan, and R. Stanley Williams of Hewlett Packard Labs in Palo Alto for showing not just how to make a Mott memristor, but that you can create controlled chaos with one. “We showed that this type of memristor can generate chaotic and nonchaotic signals,” says Williams, who invented the memristor based on theory by Leon Chua. An analysis of the material science and engineering of titanium sub-oxides as practiced by Williams at HPL for the production of standard memristors can be found in one of my old blog posts (http://www.betasights.net/wordpress/?p=1006).

Cross-section TEM of a Mott memristor composed of 8nm niobium dioxide layer between top layer of titanium nitride and bottom pillar of titanium nitride. (Original Image: Suhas Kumar/Hewlett Packard Labs, color commentary by Ed Korczynski)

Cross-section TEM of a Mott memristor composed of 8nm niobium dioxide layer between top layer of titanium nitride and bottom pillar of titanium nitride. (Original Image: Suhas Kumar/Hewlett Packard Labs, color commentary by Ed Korczynski)

The Figure shows a cross-section of a single Mott memristors formed by the region of the 8nm thin niobium dioxide (NbO2) layer that is between the 70nm diameter titanium-nitride (TiN) pillar functioning as bottom electrode and the blanket TiN layer functioning as top electrode.

Such a device exhibits both current-controlled and temperature-controlled (https://en.wikipedia.org/wiki/Mott_transition) negative differential resistance, and the proper choice of current and temperature can result in what I like to term “repeatable” chaos. It is repeatable in that a state can be controlably placed into or out-of chaos using non-linearities in electrical current-flow and temperature. From the abstract of the original article in Nature:

We incorporate these memristors into a relaxation oscillator and observe a tunable range of periodic and chaotic self-oscillations. We show that the nonlinear current transport coupled with thermal fluctuations at the nanoscale generates chaotic oscillations. Such memristors could be useful in certain types of neural-inspired computation by introducing a pseudo-random signal that prevents global synchronization and could also assist in finding a global minimum during a constrained search.

In a simulated circuit, an array of Mott memristors can be integrated with standard memristors to form a simulated Hopfield network (https://en.wikipedia.org/wiki/Hopfield_network). Hopfield nets seem to be some of the most apt models for human memory, so if we can just wire together a sufficient number of NbO Mott memristors with TiO standard memristors then we might be a step closer to functional AI.

Read the fine coverage at IEEE Spectrum:  https://spectrum.ieee.org/nanoclast/semiconductors/devices/memristordriven-analog-compute-engine-would-use-chaos-to-compute-efficiently

Or the Nature article behind paywall:  https://www.nature.com/nature/journal/v548/n7667/full/nature23307.html

—E.K.

Moore’s Law Smells Funny

…maybe we need “Integrated Cleverness Law”

“Jazz is not dead, it just smells funny.” - Frank Zappa 1973
from Be-Bop Tango (Of The Old Jazzmen’s Church)

Marketing is about managing expectations. IC marketing must position next-generation chips as adding significant new/improved functionalities, and for over 50 years the IC fab industry has leaned on the conceptual crutch of “so-called Moore’s Law” (as Gordon Moore always refers to it) to do so. For 40 years the raw device count was a good proxy for a better IC, but since the end of Dennard Scaling the raw transistor count on a chip is no longer the primary determinant of value.

Intel’s has recently released official positions on Moore’s Law, and the main position is certainly correct:  “Advances in Semi Manufacturing Continue to Make Products Better and More Affordable,” as per the sub-headline of the blog post by Stacy Smith, executive vice president leading manufacturing, operations, and sales for Intel. Smith adds that “We have seen that it won’t end from lack of benefits, and that progress won’t be choked off by economics.” This is what has been meant by “Moore’s Law” all along.

When I interviewed Gordon Moore about all of this 20 years ago (“The Return of Cleverness” Solid State Technology, July 1997, 359), he wisely reminded us that before the industry reaches the limits of physical scaling we will be working with billions of transistors in a square centimeter of silicon. There are no ends to the possibilities of cleverly combining billions of transistors with sensors and communications technologies to add more value to our world. Intel’s recent spend of US$15B to acquire MobileEye is based on a plan to cost-effective integrate novel functionalities, not to merely make the most dense IC.

EETimes reports that at the International Symposium on Physical Design (ISPD 2017) Intel described more than a dozen technologies it is developing with universities and the SRC to transcend the limitations of CMOS. Ian Young, a senior fellow with Intel’s Technology Manufacturing Group and director of exploratory integrated circuits in components research, recently became the editor-in-chief of a new technical journal called the IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, which explores these new CMOS-fab compatible processes.

Meanwhile, Intel’s Mark Bohr does an admirable job of advocating for reason when discussing the size of minimally scaled ICs. Bohr is completely correct in touting Intel’s hard-won lead in making devices smaller, and the company’s fab prowess remains unparalleled.

As I posted here three years ago in my “Moore’s Law Is Dead” blog series, our industry would be better served by retiring the now-obsolete simplification that more = better. As Moore himself says, cleverness in design and manufacturing will always allow us to make more valuable ICs. Maybe it is time to retire “Moore’s Law” and begin leveraging a term like “Integrated Cleverness Law” when telling the world that the next generation of ICs will be better.

—E.K.

Photoelectric measure of atomically thin stacks

A team led by researchers at the University of Warwick have discovered a breakthrough in how to measure the electronic structures of stacked 2D semiconductors using the photoelectric (PE) effect. Materials scientists around the world have been investigating various heterostructures to create different 2D materials, and stacking different combinations of 2D materials creates new materials with new properties.

The new PE method measures the electronic properties of each layer in a stack, allowing researchers to establish the optimal structure for the fastest, most efficient transfer of electrical energy. “It is extremely exciting to be able to see, for the first time, how interactions between atomically thin layers change their electronic structure,” says Neil Wilson, who helped to develop the method. Wilson is from the physics department at the University of Warwick.

Wilson formulated the technique in collaboration with colleagues at the University of Warwick, University of Cambridge, University of Washington, and the Elettra Light Source in Italy. The team reported their findings in Science Advances (DOI: 10.1126/sciadv.1601832).

—E.K.

ASM’s Haukka ALD Award

Dr. Suvi Haukka, executive scientist at ASM International, located in Finland, was awarded the ALD Innovation prize at the ALD 2016 Ireland conference (Figure), as chosen by the conference chairs. Haukka has had a lifetime career in Atomic Layer Deposition (ALD), starting at Microchemistry Ltd. with ALD pioneer Dr. Tuomo Suntola in 1990, and now holding over 100 patents.

Conference co-chairs Simon Elliott, Tyndall National Institute of Ireland (left) and Jonas Sundqvist, Lund University of Sweden (right) acknowledge Suvi Haukka from ASM International N.V. (center) as recipient of the "ALD Innovation Prize" at the 16th International Conference on Atomic Layer Deposition (ALD 2016) held last month in Dublin, Ireland. (Source: ALD 2016)

Conference co-chairs Simon Elliott, Tyndall National Institute of Ireland (left) and Jonas Sundqvist, Lund University of Sweden (right) acknowledge Suvi Haukka from ASM International N.V. (center) as recipient of the “ALD Innovation Prize” at the 16th International Conference on Atomic Layer Deposition (ALD 2016) held last month in Dublin, Ireland. (Source: ALD 2016)

Since ASM bought Microchemistry in 1999, Haukka has worked on the manufacturability of ALD processes for the semiconductor industry. Today, ALD technology is essential for the high-volume manufacturing (HVM) of advanced ICs, with growing demand for the fabrication of nanoscale 3D devices such as finFETs and 3D-NAND Flash cells.

As reported by Riikka Puurunen in his ALD History Blog, Haukka joins a short list of technology luminaries who have been previous recipients of the prize:
* 2011 Roy Gordon (Harvard University),
* 2012 Markku Leskelä (University of Helsinki),
* 2013 Steven George (University of Colorado),
* 2014 Hyeongtag Jeon (Hanyang University), and
* 2015 Gregory Parsons (North Carolina State University).

More on the ALD 2016 conference can be read in the travel report blog.

[DISCLAIMER:  Ed Korczynski and Jonas Sundqvist also work for TECHCET CA, and were co-chairs of the 2016 Critical Materials Conference.]

—E.K.