Vivek Bakshi, EUV Litho, Inc., www.euvlitho.com
Most of the papers at this year’s EUVL Conference during SPIE’s 2014 Advanced Lithography program focused on topics relating to EUVL’s entrance into high volume manufacturing (HVM). The 2014 EUVL Conference also had a record number of papers – 67 oral presentations and 66 poster sessions – for a 13% increase over last year. Although I did not see an increase in my EUVL short course students, both of my EUV books went into their second printing this year in soft cover, as the first editions in hard covers have sold out. So overall, there was a lot of continued momentum for EUVL as it moves toward HVM introduction.
Focus on Fab Matrices
In their paper, GLOBALFOUNDRIES compared EUVL and ArF immersion scanners for 20/14 nm metal lines and found equal yields for both lithography techniques. They did note an additional issue of EUV mask backside contamination, which I believe can be addressed. For 10/7 nm metal lines, they believe they need to address issues of overlay, mask defects, integration and line width roughness (LWR) through focus, in order to bring EUVL into production.
IMEC presented a preliminary cost of ownership (COO) study that concluded that at the 7 nm node, 75 wafers per hour (WPH) throughput will be needed for EUVL to show better COO than ArF immersion (ArFi) multiple patterning (MP). This throughput corresponds to 100 W of source power at the intermediate focus.
HVM-related metrics such as yield and availability (mean time to failure [MTTF], mean time to repair [MTTR], etc.) are now the focus. It was evident from the talk by TSMC, which reported ~10 W of power instead of the expected 30 W for their planned insertion of EUVL into the 10 nm node. A laser misalignment caused a source breakdown and a two-week unexpected downtime for the tool. This did not make TSMC happy, but did cause some trade journalists not known for their support of EUVL to announce that “EUVL suffers new setback” when it clearly had not. A brand new tool’s first installation in the field can be expected to have glitches and downtime; expecting anything else is not realistic. (More comments on source are given below.) TSMC also reconfirmed their commitment to bring EUVL into HVM at the 10 nm node.
Mark Philips of Intel, in his talk, outlined the 1-D grating and cuts approach of Yan Borodovsky. EUVL is the preferred choice for cuts as EUVL offers advantages in terms of number of masks and edge placement error (EPE). Intel still plans to insert EUVL at the 7 nm node in 2017, but needs a mature COO for EUVL. It will be either mix and match with ArFi MP or EUVL alone, depending upon the cost drivers. As the mix and match approach faces the issue of overlay, he presented a detailed model, developed with Mike Hanna of ASML, that identifies the root cause of machine to machine overlay values and will help minimize it. Current machine to machine overlay (EUVL and ArFi) is 5 nm but needs to be 3.5 nm at 10 nm nodes and 3.0 nm at 7 nm node. My perception is that with the amount of effort going into it, those goals can be achieved.
Hynix, in their paper on EUVL development efforts, made a comment that self-aligned quadruple patterning (SAQP) has 5x more steps than EUVL and that many multiple patterning steps take away any benefit that one can expect from it, and hence are not beneficial.
Source Technology Status
ASML currently has three NXE 3300B, HVM level scanners being installed in the field, including one at TSMC. They reported 30 W power (down from 50 W reported in the lab last year) with 100 W planned for this year and 250 W for next year. We know that TSMC had only 10 W at the time of conference. With ASML acquiring Cymer, I expected a change in how data is presented, with more realistic roadmaps. I understand that to predict the readiness of source is very hard, as there are many new technologies that may do well in the lab with a dozen PhDs fine-tuning them, but aren’t necessarily ready for the field where they have to perform 24 x 7 while being operated by technicians. Hence, it will take time to make them work in a fab.
Let me also mention Gigaphoton (GP), the other high power source supplier. In my opinion, they are ahead in technology but behind in engineering. They have a very stable 20 micron droplet technology (less debris), prepulse with dual wavelengths (less debris and higher conversion efficiency [CE]), magnetic debris mitigation (better debris control), infrared (IR) rejection collectors (improved image quality) and axial flow CO2 laser technology from Mitsubishi (1.6x more energy efficient than transverse flow). However, they have 42 W (duty cycle ?, 200 W at source and CE of 2.4%) and 16.9 W (duty cycle ?, 78 W at source, 3.9% CE) and expect their source to be ready in 2015.
I also seriously doubt that in situ cleaning alone can remove tin debris at 250 W and am ready to bet that it will need additional techniques such as magnetic mitigation and redesign of the tin delivery approach to meet the requirements. As GP sees 0.1 nm of tin deposited per million pulses, it is a lot of tin to remove.
My personal opinion is that if we can get 50 W with decent availability in the field this year for 3300 B, it will be a great achievement. 100 W will follow over the coming years and I cannot predict yet when 250 W sources will be ready. With the data that I currently have seen, I will stick with my predictions.
For 500- 1000 W, I think it is a good idea to look at alternate technologies such as accelerator based sources. Zeiss and Helmholtz Zentrum presented a paper on free-electron laser (FEL) based sources for 13.5 and 6.5 nm. (They first presented this idea in 2012 in my Dublin Source Workshop. I plan to have a special session on accelerator based sources again this year, as I did in the 2011 Dublin Source Workshop. ) This idea has merit and although €200 M potential price tag may have scared most people, I think the cost can be brought down. It is now time to theoretically investigate various accelerator approaches and identify difficult challenges, feasibility and roadblocks.
Out of Band (OOB) Radiation
Last year I reported on top coat approaches, which have used by chip-makers to remove OOB radiation that reaches the wafer to improve image quality. However, this comes with up to a 15% loss of photons, extra processing costs, and outgassing. An alternate idea is to incorporate OOB filtering in the collector, as presented by Eric Louis of FOM Institute DIFFER. Maybe this or something similar can be added to IR rejection that GP has built into its source collectors.
ASML is putting together 11 NXE3300 B tools (with three delivered) and has started work on next generation scanners of NXE3350B. These introduce a new parameter of non-correctable error (NCE) for optics. It is 0.7nm for 3300B and will be 0.4 nm for 3350B. With their flex pupil approach, they reported 16 nm L/S data with 10% exposure latitude.
TSMC reported in their talk that particles are generated during the exposure process, fall on the mask and need to be cleaned. It is not a surprise, as EUV photons generate particles when they react with background contamination. These particles are not captured in the particle adder test that was reported by ASML. More important than deciding who needs to be responsible for cleaning the defects (OEM or chip-maker) is to come up with a solution. We already see that pellicles offer a potential solution. ASML reported 70 nm film (60 nm pSi with caps of SiN on both sides) on a frame with 82% transmission, 106 x 139 mm2 (full size in a holder) and 1.4% average variation in intensity across the pellicle. It has been tested for 120 W of source power. There is still some possibility of generation of contamination between pellicle and mask, addition of particles during installation, lifetime and OOB reflectivity of pellicles. I expect these topics to be addressed with time.
High NA Scanners
Starting at 7 nm, a decision has to be made on going with either high NA of 0.5, or with EUV at 0.33 NA and double patterning. At < 7 nm, scanners with >0.33 NA will be needed. High NA will increase the incident angle on mask, resulting in excessive H-V bias and poor image quality. So the industry has to decide on various potential options, which include going from six to eight mirrors in scanners, mask size change from current 6 to 12 inches, and quarter- to full-field exposure options. Currently there is no common ground among OEMs, mask makers and chip-makers, but a consensus is expected to be reached by year-end, as pointed out by Patrick Kearney of SEMATECH, who presented COO for various options.
Meanwhile, Zygo has made significant progress in building high NA optics (0.5) for a micro exposure tool. Wave front error (WFE) is < 1 nm and flare is 2.5% (0.5 nm). Kevin Cummings of SEMATECH presented his plans for getting the tool ready this year for 9 nm exposure with 5 x magnification. I believe that a high NA approach will be demonstrated without issues – it just needs to be decided what other options on scanner and masks we will go with.
Toshiba called for development of 6-inch masks that can support 0.55 NA with 4x magnification and full field exposure. However, I do not know yet if we can make them to deliver acceptable imaging quality.
Mask papers mostly remain focused on addressing defectivity, with excellent contributions from SEMATECH on many fronts. Efforts in mask cleaning are making progress with reduction in damage from cleaning. What I found most interesting was the Pareto of sources of defects on substrate and masks. The planned Veeco tool upgrade will help address many of the mask blank defects. Mask defects can be either cleaned, repaired or avoided during mask patterning to provide acceptable mask yields. To avoid defects, mask patterns can be shifted or rotated during patterning. Puneet Gupta of UCLA had a third option calling for independent shifts and rotation of individual dies, which can yield 60% better yield for up to 40 printable defects (taken as 2 nm high and 50nm wide in his theoretical study). It will be a difficult solution to implement, but will it be more difficult than alternative options?
The AIMS tool from Zeiss is now taking data and can review the printability of 30-45nm defects (7-11nm at wafers) with plans to deliver the tool in 2015. SHARP microscope is up and already supporting customers at Lawrence Berkeley National Laboratory (LBNL).
For patterned mask inspection there was no update from KLA on the actinic pattern mask inspection (PMI) tool, and in general I heard no great push for getting the actinic PMI tool ready either. On the other hand, e-beam inspection for patterned mask is making good progress, with Ebara (funded by EIDEC) reporting capability to detect 28nm defects, and 16nm detection capability coming soon. IBM reported good progress in e-beam based mask inspection and using the Hermes Vision tool, and can detect <10 nm defects on wafers.
I understand that without bright mask metrology sources, tools for actinic inspection for mask defects are not going to make progress in throughput. Although we can do the job via non-actinic inspection for now, it will be not wise to continue accepting a lack of progress on metrology sources, as these tools will be needed at 7nm and below.
Resist is finally coming to the rescue of lack of source power and will become a key enabler of EUVL. It is also clear that in addition to resolution, LER and dosage, outgassing requirements must be met by resists.
I found a good bit of progress on the topic of outgassing: a paper by TSMC on prediction of outgassing of a given CAR resist; Tarutani (Fuji file) noted that outgassing is related to deprotection mechanism; progress in identifying reasons for variability of outgassing measurements in benchmarking by NIST; and analysis of non-cleanable (by hydrogen) contamination by EIDEC. As it turns out, iodine is the biggest culprit, with sulfur a distant second, as the reason for non-cleanable contamination. U Albany showed that outgassing is directly proportional to 5 times Eo (dose to clear) and the top 20 nm of resists contribute to outgassing. IMEC showed that in outgassing studies, electron beam (EB) and EUV studies can be made to be equivalent for a given setup.
There was a great deal of progress reported on understanding and improving the chemically amplified (CAR) resists by Osaka, Intel, Dow, JSR and TOK, but I found results on non-CAR resists to be even more exciting. There was impressive work on non-CAR resists and I will discuss only those with low dosage requirements. Most are based on various metal oxides, added to increase EUV sensitivity. Impria presented resists with HfO2 with 3-4 x sensitivity and with SnO2 5-8 x sensitivity greater than CAR. SUNY at New Paltz also showed results for resists with various metal clusters in a large study. The Cornell (Chris Ober) group presented results of 1.4 -1.6 mJ of ZrO2 with 5-7 nm LER and with HfO2 with 2.5 mJ sensitivity with 3-5 nm LER! I found this to be the highlight of the conference, although potential contamination from various metals still needs to be evaluated The Indian Institute of Technology (IIT), my alma mater from India, had a paper on non-CAR chemistry with 10 mJ resist with 1.8 nm LER.
Status of my Lotus bet with Lithoguru: Although Chris Mack lost his side of the bet (no EUVL papers in 2011 SPIE AL), I still have to win my side of it, which called for HVM introduction by the end of this year. If EUVL is used this year to start developing a product that eventually sells in the marketplace, I will consider myself the winner. As TSMC is the only one who is officially moving this year into HVM, let us see how their development unfolds.
Most interesting word uttered in the conference: lagniappe (pronounced LAN-yap). Charlie Tarrio of NIST used it to describe an unexpected benefit in the alignment of his EUV reflectometer for measurements of reflectivity on a collector, which was bit larger than allowed in his chamber.
Most interesting Acronym: LOVE, for local overlay error budget, used by ASML to describe their model for improving machine to machine overlay.
Uncalled for comments on EUVL by someone in media: still tasteless and unprintable.
Knee-jerk reaction: a 5% drop in ASML stock on reports of damage to a CO2 laser at TSMC due to misalignment (which took two weeks to repair, as it is an installation and service issue and not a technical challenge).
Surprising paper: Final presentation of the conference by Tagawa-san of the University of Osaka, showing that by using his “EUVL sensitizing chemical” combined with UV flood exposure, EUV and EB resist dose requirements can be drastically reduced. He showed an example of an 8.8 x increase in the sensitivity for EB resist for 75 nm L/S. I believe we should investigate what this approach can do for us in EUVL.
Most Progress: In the low dosage requirements of new metal based EUV resists. If we can go from 15 mJ to 1.5 mJ (Cornell’s results), we will need 10 x less source power. I can drink to that!
My Wish: For EUVL to become a workhorse in our fabs by 2017, just like my van with the EUVL license plate has been at my household for many years now.
With all the difficulties of lithography today, how about work on proton-beam lithography? It’s somewhat of a rare beast, and historically it has never been production worthy. However, work I’m doing now seems to say we can do 100 wafers and hour with a direct-write system comprised of 250,000 individual accelerator channels on a 100nm pitch per chip (about 26mm x 35mm). And, no masks.
Great review and summary! Nice job Mr. Bakshi..
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