Power management ICs for green energy applications

Executive Overview

The power management IC (PMIC) has become a critical component in virtually every electronics product today. Much of this demand is being fueled by the global transition to green energy solutions. Highlighted will be a 0.18µm BCDMOS process with 30V LDMOS transistors having an Rsp of 20mohm-mm2, dense 1.8V CMOS logic, well-characterized 5V analog components, and embedded non-volatile memory. Process modularity will be discussed in terms of maximizing designer flexibility, enabling both simpler, low-complexity PMICs as well as the more complex SoC solutions.

Lou N. Hutter, Dongbu HiTek, Seoul, S. Korea

In today's energy-hungry world, the watchword is green. The drive to minimize our use of energy and prudently harvest it has become pervasive. Semiconductor technology has become increasingly critical for monitoring, optimizing, and controlling electronic system power parameters in real time. At the heart of almost every electronic system is a power management IC (PMIC), so it is not surprising that the push for green energy solutions continues to spur a surge in PMIC applications and prospects for overall market growth (Fig. 1).

Figure 1. Power management market forecast. Source: iSuppli, Q4-2010

PMIC perspective

As each electronic system interconnects various IC and discrete components to achieve some overall function, each component must satisfy certain operating conditions to work properly. One such operating condition is input voltage, with some components requiring 1.2V, some wanting 3.3V, others needing 5V, and so on. One function of the PMIC is to provide these different bias levels for the other components in the system.

Each electronic system typically involves some type of input and output – as it samples some parameter, such as temperature, air/fuel mixture, etc., converting it into an electrical signal that then is electronically manipulated and fed into a microprocessor, DSP, microcontroller, or some other type of logic function. The logic function analyzes the data and makes some decision, which then is converted into an output signal to control the original parameter or some other parameter. This process requires power to be supplied to the individual components, as well as to the load. The power supplied to these other chips, or to the load for the system, comes from the PMIC.

PMICs can be simple or complex, depending on the application, and also depending upon how the system is partitioned. In some highly integrated systems, the PMIC can be very complex, containing the logic intelligence and analog control circuitry as well as many voltage regulators capable of supplying amps of current. At the other extreme, some PMICs can be very simple, handling just the voltage regulator function for the system. The semiconductor process technology required to address these two divergent applications must, itself, be flexible.

Many of today's products are portable, so battery life is very important. This means high-efficiency PMICs are critical. The broadest and strongest market demand is for PMICs that operate in the 5V to 24V range. Accordingly, we will now focus on exploring the process technology needs in this space.

PMIC process technology requirements

First and foremost, PMICs must deliver power, typically in the form of current, to a load device – e.g., an engine valve, or a headphone speaker, or an LED element. To do this efficiently, PMICs must dissipate very little on-chip power, which is typically resistive. A key factor in improving efficiency is to deliver the current with the lowest specific ON-resistance possible.

PMICs must also execute both digital logic functions and analog control functions. Power delivery is generally implemented with LDMOS (lateral double-diffused MOS) transistors, while logic functions are best implemented in CMOS. Analog control is typically done with a combination of CMOS, bipolar, and passive components. Hence, a BCDMOS process is well suited for implementing PMICs. Let's now take a closer look at a low-voltage (24V) BCDMOS process in terms of the attributes it provides to implement high-efficiency PMICs.

Today's state-of-the-art BCDMOS processes are typically based on 0.18µm lithography, thereby providing a good balance between component density and cost-effectiveness. The centerpiece component in any BCDMOS process is the LDMOS transistor. It typically performs the function of a high-current switch – providing nearly zero resistance in the ON-state, and almost infinite resistance in the OFF-state. The cross-sectional view of an n-LDMOS transistor (Fig. 2) shows a high-side device style, allowing the source/backgate to be pulled high while the substrate is tied to ground, with punch-through prevented by means of the N+ Buried Layer (NBL) placed between the two P-regions. A low-side device, by comparison, is one where the source/backgate is tied to ground, the same potential as the P-type substrate, so there is no voltage difference between the two regions and, correspondingly, no need for the NBL.

Figure 2. Cross-sectional view of a high-side (HS) n-LDMOS.

While LDMOS performance is important in PMIC designs, there are additional considerations that determine the usefulness of a BCDMOS process. In power designs, there is a lot of analog control circuitry for such things as over-temperature and over-current controls. This can involve sophisticated analog circuits where requirements such as transistor noise, parameter matching, stable reference voltage, the ability to isolate sensitive nodes from substrate noise, and temperature coefficients can become important. Hence, the process developer must focus on these things in parallel with the effort to optimize the power components. Accordingly, an optimal BCDMOS process for implementing PMICs requires the judicious integration of Bipolar, CMOS, and LDMOS technologies – with designers expecting high performance in all categories.

Modular, flexible low-voltage BCDMOS

To better illustrate the technology needed to build today's PMICs, it is useful to show an example. Dongbu HiTek's BD180LV process is a 0.18µm BCDMOS technology rated to 30V operation. It combines 30V n-LDMOS with dense 1.8V CMOS logic and well-characterized analog components including 5V analog CMOS, bipolar transistors, and passive components, providing a rich set of components for designers to use. This 24V process strikes the right balance among power performance, reliability, and process complexity parameters.

Significantly, the BD180LV was developed by starting with an existing 0.18µm analog CMOS process – the AN180 – and then by adding the necessary modules to create a robust yet flexible mixed-signal process. As a result, the foundry-compatible 1.8V and 5V logic, as well as the passives, are exactly the same across the two processes, allowing IP portability across the nodes. This enables designers to ‘step up' from an analog CMOS product design to a BCDMOS product design without having to start from scratch. All the necessary and exhaustive characterizations of the analog CMOS process translate directly into the analog in the BCDMOS version.

As can be seen in the n-LDMOS performance (Fig. 3), the BD180LV process provides best-in-class RSP performance based on reported data. In the figure, it should be noted that two versions of BD180LV are shown – with and without Epi/NBL. The non-Epi/NBL version is for cost-sensitive applications and can easily run on a conventional CMOS logic line, while the standard Epi/NBL version is for the more conventional and rugged applications and requires some specialized tools that are well-known to analog-savvy chip designers.

Figure 3. Comparison of Rsp across various LDMOS transistors.

The LDMOS device must operate over a wide temperature range, from -40C to +150C, even up to +180C for automotive applications. The statistical variation of parameters, such as BVDSS, the OFF-state breakdown voltage, makes it important to achieve ample breakdown above the desired operating voltage (VOP). Not just BVDSS, but BVON, the ON-state breakdown voltage, must remain above the VOP point to avoid potential destructive behavior in the device. As a result, a VOP-rated device often has a BVDSS 25% to 30% above VOP when measured at room temperature during the end-of-line parametric check in the wafer fab.

Referring again to Fig. 3, a 30V-rated n-LDMOS in BD180LV has a typical BVDSS of 40V, with a corresponding RSP of 20mΩ•mm2. This represents state-of-art performance in a 30V power device. It is very important to understand the margin in these devices for the application at hand. Safe operating area (SOA) testing comprehends the operating region where the device can survive, allowing the designer to push the device to higher performance levels while maintaining safe and reliable operation.

Process modularity advantages

If there is one constant in the world of semiconductor processing, it is that there can never be enough components in an analog process, even a BCDMOS process with already 80-120 components. The analog world is fractured, with niche applications abounding, which is one reason why analog is so challenging and yet resilient. Typical components for addition are p-LDMOS, for complementary power stages, isolated LDMOS, allowing low-voltage devices to be floated to high potentials, depletion MOS devices, higher levels of non-volatile memory, and a constant pressure to push the voltage bounds of the process.

Figure 4. Modularity provides flexibility to enhance analog functionality.

This is coupled with the fact that some products demand gate counts in excess of 250K, while other products have almost no logic at all. To maintain IP portability, a key enabler for design, a modular style must be adopted. As shown in the BD180LV modularity build-up chart (Fig. 4), the process starts with an AN180 base, with modules then added. The designer can tailor the process to his/her need. Each module is parametrically identical in any process flavor, so IP portability is possible. In today's world of ever-shortening design cycles, having a modular technology that offers flexibility is a welcome asset.


PMICs have become critical components in virtually every electronic system today. Demand for low-voltage PMICs continues to surge as electronic system manufacturers across the globe sharpen their focus on green energy solutions. BCDMOS has become the mixed-signal process of choice for implementing PMICs, especially when the process is modular, flexible and enables power-saving features such as the integration of compact LDMOS power transistors that reduce Rsp (specific on resistance). Today's designers of power management ICs are well advised to examine closely BDMOS processes at their disposal to determine which can most effectively combine logic density with analog and power performance.


  1. D. Riccardi, et al., "BCD8 from 7V to 70V: a New 0.18μm Technology Platform to Address the Evolution of Applications towards Smart Power ICs with High Logic Contents," Proc. of the International Symp. on Power Semiconductor Devices, 2007, Jeju, Korea.
  2. K.Y. Ko, et al, "BD180LV – 0.18µm BCD Technology with Best-in-Class LDMOS from 7V to 30V," Proc. of the Inter. Symp. on Power Semiconductor Devices, 2010, Hiroshima, Japan.
  3. P.Hower, et al., "Short and Long-Term Safe Operating Area Considerations in LDMOS Transistors," Proc. of the International Reliability Physics Symp., 2005, San Jose. USA.


Lou Hutter holds BS degrees in math and physics from Northern Kentucky U., as well as an MSEE from MIT. He is SVP and GM of the Analog Foundry Business Unit at Dongbu HiTek, Dongbu Financial Center, 32nd Fl., 891-10, Daechi-Dong, Gangnam-Gu, Seoul, 135-523 Korea; ph.: +82-32-680-4140; email: [email protected].

Solid State Technology, Volume 54, Issue 7, July 2011

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