IRT Nanoelec and CMP team up to offer world’s first service for post-process 3D technologies on multi-project-wafer

IRT Nanoelec, an R&D consortium focused on ICT using micro- and nanoelectronics, and CMP, which provides prototyping and low-volume production of ICs and MEMS, are launching a platform for multi-project-wafer, post-process 3D integration (3D-MPW).

The new and disruptive 3D configurations and assemblies created by this IRT Nanoelec/CMP initiative are designed to promote 3D integration.

This service, the first of its kind, extends CMP’s regular MPW offer by using mature 3D post-process technologies at wafer level from IRT Nanoelec. These technologies include through-silicon-vias (TSV, via last), fine-pitch vertical interconnects (micro pillar with solder) and specific finishing for 3D integration like under-bump metallurgy (UBM). These 3D modules will enable a wide panel of new, full 3D architectures, like multiple-die stacking with flip-chip, side-by-side heterogeneous integration, and 3D partitioning of different CMOS dies issued from CMP runs.

3D integration is highly complementary to traditional CMOS scaling, and has very strong potential in terms of size reduction, heterogeneous integration, miniaturization, performance improvements and, possibly, reduction of costs at the system level. The technology is now emerging in more and more applications, such as FPGA, 3D memories and MEMS, and involves wafer-level processing on dedicated runs.

The new platform provides for the first time access to post-process 3D technologies after regular CMOS MPW runs, for proof of concept, prototypes and/or small series production. This enables a large group of users to take advantage of cost division made possible, at silicon level, by the MPW regular services followed by post-process technologies. In addition, it allows 3D-MPW users to divide the cost of post processing. This benefits a large group of customers, such as universities, SMEs, research institutes and systems integrators, that usually do not have access to the 3D modules at large foundries.

These 3D post-process technologies require very limited re-design of existing chips, and will be initially used for specific CMOS nodes available at CMP. They may be extended in the future, depending on demand. CMP is responsible for supporting, checking and compiling the customer’s requests, while IRT Nanoelec, which has a very strong background in 3D integration – in particular through the institute CEA-Leti – will manage the 3D post-processing.

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