At the recent Semicon West, Suss, which supports all commercially available temporary bonding solutions, held their annual 3D workshop.
(Click on any of the images below to enlarge them.)
Eric Beyne of IMEC reported on 3D technology status. He sees:
- a clear industry convergence on Cu-TSV, vias middle with TSV dimensions 5 x 50 um. - a significant challenge is still a wafer carrier system for wafer thinning with high precision and compatible with further backside processing - as the technology matures they see a stronger emphasis on fine pitch die-to-die stacking : 40 µm Ã 20 µm Ã 10 µm Beyne sees current application focus areas as:
When looking at all the studies performed on TSVs the literature offers the following conclusions:
IMEC is moving their standard process from 5 um in 50 um thick silicon to 3 um in 50 um thick silicon. They see this soon moving to 2 um TSV in 30 um silicon which is an AR of 15. They see the standard interposer as 10 um TSV in 100 um thick silicon.Venky Sundaram of GaTech updated the audience on "Glass as an Ideal Material for Interposers, Packages and System Integration." The two interposer programs at GATech are focused on Low Cost Silicon Interposers and Packages (LSIP); (a) wafer based; (b) panel based and Low Cost Glass Interposers; (a) wafer based and (b) panel basedAccording to Sundaram glass has the following attributes:
ï»¿Although glass does have its challenges:
They see two commercialization paths for glass. They eventually see glass wafers as 2X less cost and panel based glass as 10X based glass.
Ron Huemoeller of Amkor looked at the migration of SoC to 2.5D. This can occur by breaking up large pieces of logic into smaller chips and mating on an interposer or breaking up a large monolithic die into functions and mounting on an interposer.
The former is exemplified by the now infamous Xilinx FPGA interposer development which Amkor is in the process of assembly scaling up. Amkor sees 2.5D assembly challenges as:• Die-Die X-Y Spacing
- Fillet sizes and pad metallurgy and materials
- Process assembly sequence ; Micro-join method• Die-Die / Die-Substrate Joining
- Micro bump uniformity ; Method of Join ; Materials• Thermal and Power Management
- Use of Lids, Stiffeners and Passives
- Underfill/Resin bleed, adhesive compatibility
- Process assembly sequence and materials• Warpage Control
- Interposer warpage ; Substrate warpage
- Top die warpage - area density/distribution• Intermediate e-Test Points
- Process assembly sequence
Assembly options include chip on substrate, chip on wafer and chip on chip all of which have pros and cons. This was followed by the introduction to tree new temporary bonding solutions that Suss is working on with Dow Corning, Dow Chemical and 3M. Jim Rosson of Dow Corning introduced a bi-layer, temporary bonding solution with a room temperature de-bond. This silicone solution consists of a WL-30XX Release layer and a WL-40XX Adhesive layer. De-bonding consists automated mechanical de-bonding at room temperature on Suss de-bonders The wafer is solvent cleaned on flex frame with compatible solvents and the carrier wafer is cleaned by standard processes. Dow Corning is currently expanding their beta test program of this temporary bonding system. Jeff Calvert introduced Dow Chemicals new BCB based temporary bonding solution XP-BCB.
AP-3000 adhesion promoter is spun onto the carrier wafer followed by XP-BCB onto active die wafer.
The temp adhesive is cured at 210-230C for 10-30 min. De bonding is done mechanically at RT due to the lower adhesion of BCB to the device wafer.
Blake Dronen of 3M described their next generation Wafer Support System (WSS).
Gen II WSS uses conventional WSS materials but adds a high temperature thermoplastic primer layer to the substrate surface as a surface for the UV curable adhesive to bond, independent of the wafer surface passivation material. Upon laser degradation the LTHC layer and removal of the glass , the WSS adhesive joining layer can be peeled off the primer surface in a conventional manner. The thermoplastic primer is solvent rinsed, eliminating any opportunities for residue or imparting bump damage by the peel step. This process reportedly will be ready for release in 4Q.
An LTHC free process is also being developed to simplify glass recycle and reduce overall process cost by eliminating the debonder laser. It uses the conventional WSS materials but replaces the LTHC layer with a 100% solids UV curable "release layer" that is tuned to enable mechanical separation of the carrier at the interface. The adhesive joining layer, when cured, becomes a single component with the release layer, peeled as one during debond. The LTHC free process is currently being developed and optimized.
Chris Rosenthal of Suss reported on their high throughput modular equipment platform for temporary bonding and debonding. Adhesive thickness requirements depend on the application:
Suss has concluded that room temperature lift-off debonding is fundamentally less risky than thermal slide debonding.
Suss introduced the XBC300 Gen2 for Room Temperature Debonding and Cleaning.
For all the latest on 3DIC and advanced packaging stay linked to IFTLE..................................