IFTLE 99 Electronic Design Process Symp (EDPS) focuses on 3DIC

By Garrou
A few weeks ago EDPS (the Electronic Design Process Symp) held a 3D day in Monterey CA. Riko Radojcic of Qualcomm gave a plenary on the “Roadmap for Design and EDA Infrastructure for 3D Products” and Arif Rahman, Altera, Steve Pateras, Mentor, Mac Greenberg and Bassillos Petrakis of Cadence followed in a session chaired by Herb Reiter of eda2asic, with  presentations on design and test challenges.

Radojcic showed the following Xsect as what is becoming “mainstream technology” consistent with what the recent IMAPS DPC panel had to say [see IFTLE 94, “Experts Discuss Interposer Infrastucture at IMAPS Conference”] with 5 x 50 Cu TSV and solder capped copper pillar interconnect.

(Click on any of the images below to enlarge them)

It was good to hear Radojcic comment that “there are no intrinsic process technology show stoppers for memory on logic “ and that we just needed to get into volume production so we could exercise the processes.
For memory on logic he proposed the following as the status of the design environment:

Although Qualcomm has publically stated many times in the past that they ae not fans of interposers since they will increase the size of the devices while adding cost (amongst other things), Radojcic offered the following interposer challenges:
- low cost with fab like (1um pitch) routing may be hard
- timing driven routing may be had
- pre stack test may be hard

- managing Si with floating substrate may be hard

- fitting a small form factor at system level may be hard

Rahman’s talk for Altera centered on EDA needs for FPGAs. Altera had recently announced a program with TSMC to develop   heterogeneous 3D solutions that would combine an FPGA with a customer’s intellectual property, ranging from CPUs, ASICs,  ASSPs,  memory and optics.

TSMC is providing the end-to-end CoWoS (Chip-on-wafer-on-substrate -- the internal TSMC name for their 2.5D process) process, including the front-end manufacturing of the die and the back-end assembly and test of the bare die on an interposer with TSVs connecting the bare die.
The Altera/TSMC team have developed a heterogeneous 3DIC test vehicle for this program.


The theme for Bansal and Greenberg of Cadence was that “Wide-IO is driving 3DIC TSV”

We have discussed the easoning behind and the status of wide IO in the past [see IFTLE 87, “JEDEC wide IO standards...”] . Bansal shows a nice roadmap for future wide IO standards, and shows  

why wide IO will be needed in future products:

They conclude that Cadence stands ready with EDA tools and IP to enable your TSV designs with real experiences and partnerships with ~8 test chips and 1 production chip already completed.
We have discussed the Cadence [see IFTLE 72 “2011 IEEE 3 Test Wokshop”] and Mentor Gaphics DfT [see IFTLE 83, "Orange County 3DIC Workshop"] work on DfT previously. At EDPS both Bassilios (Cadence) and Pateras (Mentor) further discussed evolving BIST and other test flows for 3DIC.  I suggest you go to their respective web pages for complete detail on these important  test options.
Follow up on Lester the Lightbulb
These supportive messages were sent to me following last week's blog:
"I started keeping receipts and writing down the dates on CFL bulbs I have purchased and so far have received three free replacements from the manufacturer as they tend to die in about a year [like incandescants] instead of 8000 hrs. This may in fact be the true savings to savvy consumers, as I may never have to buy another bulb again!!!"
“Thank you for being one of the 'voices of reason' in the LED debate.”
For all the latest on 3DIC and advanced packaging stay linked to IFTLE...........

and proposed that the following gaps currently exist.
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