SEMI forms 3D stacked IC standards group, seeks volunteers - Advanced Packaging
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SEMI forms 3D stacked IC standards group, seeks volunteers

December 7, 2010 - SEMI International is forming a standards committee to evaluate and create specifications and practices for 3D stacked ICs (3DS-IC), with initial efforts targeting three areas: bonded wafers, inspection/metrology, and thin wafer handling.

3D ICs that stack 2D die -- most popularly using through-silicon vias (TSV) -- are the next step of 3D integration beyond wire bonding and flip-chip, promising a fundamental shift for multichip integration and packaging with benefits of better performance, smaller footprints, and reduce cost and power consumption. They're are already being used in CMOS image sensors, and are expected for use in IO SDRAMs in 2-3 years. But design and mechanical complexities need to be addressed, e.g. signal interference, manufacturing defects, and thermal management.

So, SEMI and SEMATECH have been working together to gather industry input and identify potential sweetspot topics for standardization, from 3D TSV integration challenges to gaps between existing technologies and future solutions. The proposed charter for the 3DS-IC Committee is to promote mutual understanding and improve communication between users and suppliers of materials, carriers, equipment, automation systems, and devices; enhance manufacturing efficiency, capability, and shorten time-to-market; and reduce manufacturing costs.

The work will initially consist of three Task Forces:

  • Bonded Wafer Pair: This group will create a standard for BWP using the SEMI M1 spec ("Specifications for polished single-crystal silicon wafers") as a starting point. SEMATECH's Andy Rudack will lead this group.
  • Inspection and Metrology: Identify and create new standards (none currently exist) to address deficiencies for inspection and metrology created by 3DS-IC. This includes TSV depth, BWP thickness/TTV, microbump coplanarity, defect, and overlay. Leader: Semilab's Chris Moore.
  • Thin wafer carrier: Identify and create new standards (none currently exist) for thinned wafer carriers to address deficiencies created by 3DS-ICs, including thin wafer handling and carriers (e.g. automation, shipping, process). Leader: Qualcomm's Urmi Ray.

SEMATECH companies backing the effort include GlobalFoundries, HP, IBM, Intel, Samsung, and UMC; others supporting a formal 3DS-IC standards committee include Amkor, ASE, IMEC, ITRI, Olympus, Qualcomm, Semilab, Tokyo Electron, and Xilinx.

The 3DS-ICs standards committee's inaugural in-person meeting will be held at SEMI's Americas Spring Standards meeting (March 2011 in San Jose, CA). Interested parties wanting to join the committee or seeking more information can contact SEMI's James Amano ([email protected]).


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