Intel fabs highest mobility pFET with Ge channel

by Laura Peters, contributing editor

IEDM Previews:
Intel fabs highest mobility pFET with Ge channel
University of Tokyo first to demo III-V self-aligned source/drain
IBM, Macronix identify phase-change memory failure mode
Record photodiode quantum efficiency from Taiwan lab
How strain can protect devices from ESD
SEMATECH tipping III-V MOSFET, FinFET, and resistive RAM
TSMC anneal for gate-last HKMG process
Imec IEDM presentations to cover More than Moore, ITRS
When do TSV stresses affect device operation?
Multi-threshold-voltage flexibility in FDSOI
CMOS imager works from light to night
Carbon nanotube vias approach production densities
IBM Alliance simplifies pFET HKMG
IM Flash details 25nm NAND

December 6, 2010 - At IEDM 2009, Intel announced a record-breaking quantum well field effect transistor (QWFET); a 35nm gate length device capable of 0.28mA/μm drive current and peak transconductance of 1350μS/μm. These QWFETs used InGaAs as the quantum well channel material. At this week’s IEDM 2010 in San Francisco, Intel (Hillsboro, OR) will again demonstrate a first: a high-mobility germanium QWFET that achieves the highest mobility (770 cm2/Vsec) with ultrathin oxide thickness (14.5Å) for low-power CMOS applications. This hole mobility is 4× higher than that achieved in state-of-the-art p-channel strained silicon devices. These results involve the first demonstration of significantly superior mobility to strained silicon in a p-channel device for low-power CMOS.

The biaxially strained germanium QW structure (Figure 1) incorporates a phosphorus doped layer to suppress parallel conduction in the SiGe buffers. Intel used RTCVD to grow the Ge structure, yet noted that the Hall mobility matches that of MBE (molecular beam epitaxy) grown germanium QW structures cited in the literature. The transistor uses HfO2/TiN high-k/metal gate, self-aligned boron implanted source and drains, W/Ti contacts, 1.3% strained Ge QW channel and a phosphorus isolation layer. Importantly, a thin silicon cap layer prevents carrier transport out of the quantum well. Thermal cycling during transistor fabrication causes a thin oxide layer to form. Without the silicon cap, mobility is significantly degraded due to increases in interface trap density. Effective oxide thickness was scaled to 14.5Å.

Figure 1: Biaxially strained undoped germanium quantum well structure on a silicon substrate. (Source: Intel)

For reference, the Intel researchers also fabricated a relaxed Ge MOSFET with the same overall process. The plot of hole mobility versus density (Figure 2: ) shows a 4X gain with the strained germanium QW device (at ns =5 × 1012 cm-2, the value for a state-of-the-art silicon transistor channel at Vdd =0.5V).

The device achieves a subthreshold slope of 97mV/dec. Key to achieving this and other performance metrics is the use of the phosphorus isolation layer between the Si0.30.3Ge0.7 buffer layer and the device.

Figure 2: Hole mobility vs. density for strained silicon, a relaxed Ge MOSFET reference and the strained Ge quantum well FET. The data matches simulations assuming interface defect density and surface roughness matches that of state-of-the-art silicon devices. (Source: Intel)



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