IFTLE 102 “3.5D Interposers to someday replace PWBs” - TSMC; GF engaging with 3D customers; Intel predicts Consolidation

By Garrou
3.5D Interposers

At the 15th Symposium on Polymers for Microelectronics held last week in Wilmington DE, TSMC’s Doug Yu, Sr. Dir. of front end and back end technology development,  challenged the current nomenclature for interposers and suggested that the more versatile interposer technology should be called 3.5D instead of 2.5D since it is, and will be, capable of much more than the simple 3D stack.
The term 2.5D is usually credited to ASE's Ho Ming Tong who ~ 2009 (or even earlier)  declared  that we might need an intermediate step towards 3D since the infrastructure and standards were not ready yet.  The silicon interposer, Tong felt, would get us a major part of the way there, and could be ready sooner than 3D technology,  thus the term 2.5D, which immediately caught on with other practitioners.

Yu's new position is that interposer technology actually is more versatile and thus should be called 3.5D since it  not only offer a better thermal solution than 3D, but "...can  some day replace most of the high density PC boards." Yu's position is that this modular silicon technology will need minimum low density PCB substrate to connect the functions that have been fabricated on silicon and will be, in essence, the perfect "fab centric" solution. Yu proceeded to show how future smartphones and tablets could be made up of such simple 3.5D silicon modules. More from the Polymers for Electronics meeting coming soon at IFTLE.

Global Foundries 2.5/3D Announcement

GLOBALFOUNDRIES has announced the installation of TSV production tools for the company's 20nm technology platform. CTO Bartlett announced that they were  "...engaging early with partners to jointly develop packaging solutions that will enable the next wave of innovation in the industry." The first full flow silicon with TSVs is expected to start running at Fab 8 (Saratoga NY)  in Q3 2012 with mass production expected in 2014. GF is also preparing for  a 2.5D line within its Fab 7 facility in Singapore with a similar time schedule as the 3D line in the United States.

While arch competitor TSMC has announced a one-stop-shop turnkey line which includes all of the assembly and test steps traditionally handled by the OSATS [see: "TSMCrepeats call for foundry-centric 2.5/3D industry"], GF proposes to handle  TSV fabrication (Cu , vias middle) and other front-end steps while typical backend  processes such as temporary bonding/debonding, thinning, assembly and test will be done by their OSAT partners such as Amkor [ see IFTLE 65 "..... GLOBALFOUNDRIES Packaging Alliance..." GlobalFoundries reports that they will define a PDK with its partners, initially they are looking at 6 um vias on a  40-to-50um pitch.

Intel agrees - Its all in the Economics

At the recent Intel analyst day CEO Paul Otellini CEO predicted that the increasing cost of manufacturing in the IC industry would result in consolidation that  will "...only leave two or three companies at the leading edge of chip design." Otellini reports that "Gordon Moore predicted a thinning out of chip fabrication facilities once the cost of a new 200mm wafer manufacturing plant hit $1bn, but he was a little too early."

With the cost of a 300mm fab expected to exceed $5B at the 28 nm node and  450mm wafer fabs that are projected to cost more than $10B apiece few companies will have enough volume to absorb such costs.  

Readers of IFTLE know that we have been predicting this outcome for several years [ see PFTLE "IC Consolidation, Node scaling and 3DIC". Nice to see that Intel  agrees, although this will severely limit options for customes of the latest node technologies. 

If you look at this strictly in terms of economics, HVM players at 22 nm should be limited to :

Logic - Intel, Samsung, ST Micro
Memory - Samsung, Toshiba, Micron/Elpida, Hynix ?

Foundries - TSMC, GF

That's less than 10 total players on the leading edge moving forward. Better start getting used to it !

For all the latest on 3DIC and advanced packaging stay linked to IFTLE...................

Dr. Phil Garrou gives his insight into leading edge developments in 3-D integration and advanced packaging, reporting the latest technical goings on from conferences, conversations, and more.

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IFTLE 116: A6 applications processor for iPhone 5 from Samsung, but...


IFTLE 115: No nickels; SCP quals low-volume TSV manufacturing; 3D IC slowdown; Apple/TSMC timetable


IFTLE 114: 28nm capacity nickels, and a "symbiotic relationship"


IFTLE 113 An Exclusive Interview with Mr Lester Lightbulb


IFTLE 112 TSMC Staffing up for 2.5/3D Expansion ; Semi 3D Standards; Sony shows off 3D stacked Image Sensors


IFTLE 111 New Temporary Bonding Technologies Introduced at Suss 3D Workshop


IFTLE 110 Samsung Breaks Wall of Silence at DAC 2012


IFTLE 109 2012 IEEE VLSI Conference ; Lester’s cousin CFL Dies Prematurely


IFTLE 108 2012 ECTC 2: NCF, WUF, MUF for tight pitch Assembly


IFTLE 107 2012 ECTC Part 1 Committees and Awards


IFTLE 106 2012 Symp on Polymers for Microelectronics


IFTLE 105 TSMC Tech Symp; UMC Investment; Latest rumors on IBM, Intel, Samsung and Apple


IFTLE 104 IMAPS DPC Part 2; Over 50% of TI WB Converted to Copper


IFTLE 103 2012 IMAPS AZ Device Pkging Conf; Fujitsu Low Temp Cu-Cu Bonding


IFTLE 102 “3.5D Interposers to someday replace PWBs” - TSMC; GF engaging with 3D customers; Intel predicts Consolidation


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