Stacked silicon interconnect is better than 3D stacking, says Xilinx - Advanced Packaging
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Stacked silicon interconnect is better than 3D stacking, says Xilinx

By Debra Vogler, senior technical editor

February 8, 2011 – Xilinx' stacked silicon interconnect technology (SSIT) was first introduced in October 2010. ElectroIQ caught up with Suresh Ramalingam, director of advanced package design and development at Xilinx, at the January MEPTEC luncheon (1/12/11, Santa Clara, CA), where he gave a presentation on the technology. has published several articles about Xilinx' stacked silicon interconnect technology: 
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In a podcast interview with senior technical editor Debra Vogler, Ramalingam discusses the technical challenges associated with the company's stacked silicon interconnect technology. He noted that through silicon vias (TSVs) -- especially Cu-based TSV -- involve significant stress challenges and a key part of the solution is figuring out the material set (e.g., the liner materials) and the design space that makes this problem transparent to what needs to be done for post-processing of the interposer and the packaging. Xilinx spent about a year before it could get to a robust working solution, he said.

Listen to Ramalingam's interview here: Download (iPod/iPhone users) or Play Now

Regarding the side-by-side integration that is inherent in SSIT, Ramalingam said the company believes that it is a much better approach than 3D stacking because the thermal issue is pretty much nonexistent in the sense that the power dissipation would be more like a monolithic chip package. From an ease of design standpoint, he said that standard EDA tools can be used where the interposer is treated just like additional layers in the design of the silicon.

The company is currently working on a 28nm test vehicle, and they already have first packages back. Process qualification work is expected to be completed within the next quarter or two.    

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