Experts Discuss Interposer Infrastrucrure at IMAPS Conference

By Garrou
IFTLE brought together a  panel of manufacturers, users and market specialists at the 2012 IMAPS Device Packaging Conference in Fort McDowell AZ to discuss the Evolving 2.5D / 3D Infrastructure. [ Douglas Yu, Sr Director of front end and back end technology development for TSMC; Jonathon Greenwood, Director of Packaging R and D at GlobalFoundries;  Remi Yu, Deputy Division Director of UMC]memory suppliers [Nick Kim, VP of future electronic packaging technologies at Hynix] assembly houses [ Rich Rice, Sr VP of sales for ASE and Ron Huemoeller, VP of Advanced 3D interconnect at Amkor] users [Matt Nowak, Sr Director of Engineering at Qualcomm] and Market specialists [ Jan Vardaman, President of TechSearch Inc].

(Click on any of the images below to enlarge them)

       [l to r] Doug Yu [TSMC], Garrou [IFTLE],Huemoeller [Amkor], Vardaman [TechSearch],
Greenwood [GlobalFoundries], Yu [UMC], Kim [Hynix], Nowak [Qualcomm], Rice [ASE]

When asked whether 2.5/ 3D TSV technology has been narrowed down to copper TSV middle from IDM or foundries and some vias last backside all the panelists agreed with this conclusion. When asked about standard TSV dimensions, the foundry and OSAT representatives all agreed that 5-8 µm  on 50 µm thick Si looks like it has become the standardized offering that many of their customers are expressing interest in. When it came to interposers, they similarly all gave the nod to 100 µm thick interposers with ~ 10 um diameter TSV. 
Sourcing Interposers
A significant portion of the panels time was spent discussing current and future interposer sourcing. Assuming the attributes of “fine”vs “coarse” interposers as defined in the table below, the question becomes “where will these interposers be coming from” and “what will they be used for” ? 

So far announcements from Xilinx and Semtech indicate that they will both be using “fine pitch” interposers i.e fabricated by ~65 nm dual damascene [DD] CMOS processing by TSMC and IBM respectively. Altera and Nvida have also announced similar high density interposers for future use as have other graphics chip makers.
While all the OSATs have RDL technology capable of fabricating “coarse” interposers so far none of the major players [ ASE, Amkor, SCP, SPIL] have announced that they are entering the interposer business.

While all of the current roadmaps point to 2012-2014 as being the date for initiation of mass production for 2.5/3D products one must now ask where is the interposer production to meet this demand. If these lines are not in place now, is it easonable to think that products using them be qualified and in mass production within the next 24 months ?
During his conference presentation Amkors Huemoeller indicated that they would not be manufacturing interposers and their search of the industry for sources  indicated that only 3 players were close to being ready to deliver interposers that wee useful to Amkor, namely TSMC, UMC and GlobalFoundries.
 While glass panels and even possibly advanced laminates presented interesting possibilities for low cost future products, Amkor’s perspective is that  they are in the earliest stages of R&D.
All 3 of the foundry panelists indicated that they will be commercializing fine featured interposers although as we stated only TSMC and IBM had announced small volume product production has been initiated.
When asked about rumors circulating that OSATS are looking to put equipment in place to manufacture DD “fine pitch“ interposers, both Amkor and ASE indicated that they had no plans to do so.
IFTLE concludes that despite significant “industry chatter” the only programs that can afford interposers, so far, are programs that require the density or other attributes provided by fine featured interposers which can only be provided today by foundries /3D active IDMs. While we can anticipate that there might be products in the future that can be designed to take advantage of “coarse” interposers, and some of the initial fine interposer activities such as memory + logic + graphics chip applications might be able to migrate to coarse interposers as they become available, we will, initially at least, be limited by the availability and cost of foundry supplied interposers. 
The Evolving Infrastructure
TSMC reconfirmed  that they will provide full 2.5 / 3D service including chip design and fabrication, stacking and packaging [ see “2.5D announcements at the Global Interposer Techconferenceand “TSMC repeats call for foundry-centric 2.5/3D industry” ]
TSMCs Yu indicated that they have made their thoughts clear in the past few months and it can be found clearly delineated on their web page. During his plenary lecture Yu once again indicated that fabrication of chips on interposers was not as easy as making prototypes makes it look and they strongly favored controlling and being responsible for the full process.
When asked about supplying memory needs, Yu indicated that they would also handle that by having partnerships in place to supply the required memory although these partners were not identified.
When asked for their positions, UMC and Global Foundries indicated a preference to work under the open ecosystem model where chips from various vendors could be stacked and assembled by OSAT partners.
When asked how the current economic issues surrounding Elpida was affecting the UMC/Elpida/PTI partnership, UMCs Remi Yu responded that this was only one engagement that they had in place for 2.5/3D and that they were moving forward with others.
Amkor’s Huemoeller indicated that foundries would be supplying interposers and they [ the OSATS] would be assembling them.
 ASE agreed short term but indicated that longer term they envisioned a broad “pie” with space for several types of players. ASE envisions future applications where coarse interposers would find their niche and be an important part of the technology base
Both of the OSATS, as would be expected, favored the open ecosystem model where chips from various suppliers would be assembled at the OSATS. 
Qualcomm reiterated a position that they have expressed in the past which is that interposers would add substantial cost to 3D stacking and as such probably would not be a broadly accepted solution for low cost mobile products
TSMCs Yu responded that indeed the addition of an interposer added cost to  the overall component, but that “...this [2.5D] solution also offers cost savings by reuse of IP and separating digital and analog circuitry and allowing partitioning of costly SoC “ and that this in fact could make it the lowest cost solution..
When Hynix was asked whether they would be offering memory stacks containing TSV as have been already announced by Samsung, Micron and Elpida Hynix Kim responded that he expects “2 and 4 chip memory stacks with TSV to be in mass production in 2013”
When the panel was asked with the wide IO memory standard is now in place. what other standards were needed quickly Nowak of Qualcomm indicated that the upcoming Semi handling and transport standards were needed and noted that standardization was also needed in the ESD area and  standardization in the “design exchange formats” where he feels Si2 is taking the lead.
When asked for their opinion on the current status of design tools all 3 of the foundries indicated that current design tools are adequate to move forward. Qualcomm’s Nowak offered that logic on logic design tools were still lacking.
In terms of test strategies UMC would like to see some better standardization in the test area while Yu of TSMC drew a chuckle from the crowd when he noted that test needed to be minimized. Similarly, on the assembly front Rice indicated that ASE is having to test “everything” till the yields are up and Amkor quickly concurred.
Focusing on the first generation of 2.5/3D  stacking interconnect all accepted that this will be done with Cu/Sn eutectic by reflow or thermo-compression bonding.   When asked what was limiting direct Cu-Cu bonding all agreed that copper bonding was not ready for prime time just yet. Yu a strong proponent of copper interconnect, noted that current copper bonding options have yield issues that have not yet been overcome “current requirements for pads are too large and the required CMP of the interfaces is causing dishing that must be handled...HVM of copper –copper bonding options is tougher than showing research samples”
When similarly asked about  hybrid metal/oxide bonding schemes where oxide / copper surfaces are polished flat, oxide bonded then subsequently oven annealed to strengthen oxide bond and form Cu-Cu bonds (as shown by Ziptronix and Leti) no panel members were willing to say that this technology was close to commercialization.  TSMC responded that these technologies required very flat surfaces which were difficult to obtain due to dishing and other issues and that in general such technologies were “not ready right now”.  ASE expanded that this option was not required to solve todays problems and therefore was being looked at as a interesting R and D solution which could find its niche later. During Q and A Cook of Ziptronix offered that she thought their technology was ready and simply awaiting the commitment of a significant player. When the panel questioned copper migration issues due to miss alignment of the Cu-Cu bonds, Cook offered that their process which encapsulates the copper pillars in nitride barrier. 
Rumors abound that TSMC is designing the apple A6 processor for ipad and iphone with 3D TSV. When asked to comment on this or whether Samsung was also offering TSV in their design of the A6 this question brought the expected “no comment” from TSMCs Yu and silence from the rest of the panel. Similarly no one would offer up comment about who would be supplying Sony who announced that they would require TSV interposers for their next Playstation upgrade.
When asked about timing for the expected HVM of wide IO memory stacks for tablets, Qualcomm responded probably 2013 and Hynix responded maybe 2015.

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