by Dr. Phil Garrou, contributing editor
December 15, 2010 - With a general consensus that CMOS is becoming economically if not technically less and less viable as the industry continues to scale, it is to be expected that we will be seeing more and more 3D IC presentations at IEEE's premier device conference, the IEDM (International Electronic Devices Meeting).
During his keynote presentation, Jim Clifford, SVP and operations GM at Qualcomm, indicated that scaling was becoming to expensive and therefore the company was backing 3D through-silicon via (TSV) technology. He urged the rest of the industry to "collaborate on 3D IC and invest in its infant infrastructure."
Conventional scaling has become more challenging in terms of materials, patterning and electrical performance, and now requires huge capital investments, noted Kinam Kim, president of Samsung Advanced Institute of Technology (SAIT), in his keynote presentation on the future of silicon technology. Current scaling strategy, he said, "is almost unusable for the 10nm node."
Kim expects mobile processors, FPGAs, and high-performance ASIC applications will require more functionality at greater speeds, which will necessitate "a heterogeneous device stack with a wide I/O interface and high data rates." 3D IC technology, he noted, is being adopted "as a promising solution for these devices."
In a presentation on 3D integration for the 28nm node and beyond, TSMC researchers indicated they have successfully integrated 3D technology into advanced CMOS foundry processes, described as "a major step toward 3D production."
Of special interest are the TSMC studies on Cu protrusion and its effects on device fabrication and reliability. As the system cools down from thermal excursions, mismatches in CTE between Si, SiO2 liner, and Cu introduces two un-desirable effects:
- Cu extrusion around the center of the TSV. They find that protrusions depend on several process parameters, including the electroplating processes (ECP), electrolyte selection, impurities co-deposited with Cu, Cu grain size distribution, and post deposition annealing conditions.
- Liner cracking. Having the smallest CTE, the oxide liner undergoes high stresses exerted by the Cu TSV and the Si substrate. The maximum stress concentration is found to be near TSV bottom, where the majority of liner cracks were observed that causes significant current leakage. TSMC has reportedly found solutions to these issues which strongly impact chip yield.
3D-induced stresses are one of the key constraints in a 3D design flow that must be controlled in order to preserve the integrity of front-end devices. IMEC and some of their consortium members (Panasonic, Qualcomm, Samsung) examined the stress induced by single- and arrayed TSVs, quantifying the stress distribution and determining its impact on both analog and digital FEOL devices and circuits. They conclude that stress aware design and accurate keep-out-zone (KOZ) dimensions will be needed to optimize silicon usage.
From stress modeling and experimental data, the IMEC consortium has developed transistor KOZ for both digital and analog circuits. The IMEC researchers conclude that the KOZ for a large matrix of TSVs is over 200μm for analog circuits and 20μm for digital circuits, and add that the complex interaction of stress components makes it difficult to use simple design rules without sacrificing large layout area. Depending on the TSV footprint and the number of TSV required, different TSV placements will be optimum (single, row, matrix).