Cadence delivers the first broad cloud portfolio for the development of electronic systems and semiconductors

Cadence Design Systems, Inc. (NASDAQ: CDNS) today launched the Cadence Cloud portfolio, the first broad cloud portfolio for the development of electronic systems and semiconductors. The Cadence Cloud portfolio consists of Cadence-managed and customer-managed environments that enable electronic product developers to use the scalability of the cloud to securely manage the exponential increase in design complexity. With the new portfolio offerings, customers gain access to improved productivity, scalability, security and flexibility, through scalable compute resources available in minutes or hours instead of months or weeks, achieving better overall throughput in the development process.

The announcement was made at the 55th annual Design Automation Conference (DAC) being held in San Francisco at Moscone Center West, June 25-28, 2018. Cadence is located in booth 1308 in the main exhibit hall and booth 1245 in the Design Infrastructure Alley. For more information on the new Cadence Cloud portfolio, please visit www.cadence.com/go/cadencecloud.

Cadence gained extensive cloud experience by hosting design environments for more than 100 customers of varying sizes and architecting many of its products to be massively parallel for improved scalability in the cloud.

“The cloud will fundamentally influence silicon design by giving semiconductor companies the ability to optimize their capital versus operational expenses for computing infrastructure,” said Suk Lee, senior director Design Infrastructure Marketing Division at TSMC. “Cadence has passed our rigorous cloud security audits and is authorized to engage with mutual customers on the Cadence Cloud using TSMC process models and rule decks.”

“While many industries have previously adopted the cloud to address compute-intensive workloads, systems and semiconductor companies have faced unprecedented challenges that have made cloud adoption difficult until now,” said Richard Wawrzyniak, principal analyst for ASIC & SoC at Semico Research Corp. “Some of the challenges included security concerns and the sheer amount of design data and the inherent scalability limitations with electronic design automation tools. The Cadence approach to the cloud addresses historical industry issues, opening the door for customers to adopt the cloud and enter the next generation of chip design development.”

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