Performance enhancements for multi-die DRAM packages

Executive Overview

Three variations of the opposing face wire-bonded DRAM dual-die package (DDP) were developed and compared to the standard DDP using live DDR3 die and a high-speed production memory tester. The devices were tested on a production memory tester in shmoo plotting mode to assess their electrical performance using data rates between 1600MT/s and 1866MT/s. The copper coupon experimental legs exhibited the best overall performance offering a 9.2% improvement in data eye width versus the conventional DDP control.

R. Crisp, W. Zohni, B. Haba, Tessera, San Jose, CA USA; W. Chang, W. Fan, S. Chuang, Powertech Technology Inc., Hsinchu, Taiwan, R.O.C

Three variants of an opposing face wire-bonded DRAM dual-die package (DDP) were developed and compared to the standard DDP using live DDR3 die and a high-speed production memory tester. Each of these variants incorporated ground reference structures adjacent to the long bond wires of the top die. Two of the experimental legs used copper coupons attached to the top surface of the face-up top DRAM die with bond wires passing over this reference plane. One of these legs left this reference plane electrically floating while the other had the reference plane wire-bonded to ground on the substrate and also wire-bonded to the DRAM die to supply VSS to the die to reduce the ground inductance. The last experimental leg used a silver-epoxy compound to over-mold the wire-bond encapsulation with this over-mold electrically connected to the substrate ground to provide a ground reference structure atop the bond wires. The devices were tested on a production memory tester in shmoo plotting mode to assess their electrical performance using data rates between 1600MT/s and 1866MT/s. The copper coupon experimental legs exhibited the best overall performance offering a 9.2% improvement in data eye width vs. the conventional DDP control.

Because of signal integrity concerns, fan-out of memory modules on memory channels limits the clock frequency of two-socket DIMM-based DRAM memory systems to ~1333MT/sec. By reducing the loading to a single DIMM, higher operating frequencies beyond 1600MT/sec are attained.

This limitation of DIMM modules/channel trades off memory capacity for memory clock frequency. As a result, higher capacity DIMM modules are desired to avoid memory capacity limitations. Today's leading-edge monolithic DRAM die are limited to 4Gbit capacity. Using 32 such devices on a memory module limits the capacity of the module to 16GB. To extend beyond this requires higher capacity devices, typically implemented in multi-die packages such as the dual-die package (DDP).

Difficulties with current DRAM DDP

DDP DRAM devices generally operate at reduced clock rates vs. single-die packaged DRAM due to lengthy top-die bond wires on signal and power leads. The power leads suffer from high inductance in the current-carrying path causing excessive noise on the chip's power buses. The power bus noise limits the operating frequency and degrades the operating margin of the devices [1, 2].

A further reduction of operating frequency arises due to the excessive bond wire length associated with the switching signals in the standard wire-bond DDP package design. This bond wire configuration suffers from both increased inductance vs. standard single die packaging, as well as impedance discontinuities arising from the configuration of the bond wires lacking a suitable ground reference plane. The goal of this work was to develop an improved DRAM DDP using existing wire-bond manufacturing infrastructure and measure its performance improvement.

Design of experiment

In previous work [3] it was reported that S-Parameter simulations of face-up wire-bonded structures provided guidance for the experimental legs to be fabricated. In addition to a conventional opposing-face wire-bonded DDP control, three additional experimental legs were constructed and measured (Fig. 1).

Figure 1. Control (leg 1).

The second experimental leg was a conventional DDP, but over-molded with a conductive epoxy connected to ground. The third experimental leg was a conventional DDP, but with electrically isolated copper coupons attached to the top die surface under the bond wires (Fig. 2). The last leg was similar to the third experimental leg, but copper coupons were wire-bonded to the substrate ground and to the VSS pads on the die (Fig. 3).

Figure 2. Floating copper coupons attached to top die (leg 3).
Figure 3. Grounded copper coupons attached to top die (leg 4).

The height of the 0.7mL bond wires above the reference plane for legs 3 and 4 was set at 50µm for manufacturing reasons, resulting in an impedance of ~72 ohms (Fig. 4).

Figure 4. Impedance of wire over reference plane.

Ten units of each leg were fabricated using high-speed 2Gbit (x8 organized) live DDR3 die and tested for functionality. Each leg was then shmoo-plotted using an Advantest 5503 tester measuring data eye width (TVOH) vs. Vdd. The top and bottom die in the structures were shmooed separately to measure performance differences. The shmoo test program used a base 1600MT/s timing set with CAS latency = 11 (CAS latency = column address strobe latency, a measure of access time).

Results and discussion

Using a CAS latency of 11 cycles, all legs passed with 1600MT/s timing sets. Table 1 contains a summary of the measured results. Shmoo results for the grounded coupon top die experimental leg are shown in Fig. 5.

Figure 5. Grounded copper plane top die shmoo (5ps/div).

Several factors combine to determine the maximum speed that a DRAM can operate. Of utmost importance is the die itself. As a general rule, the more aggressive the wafer fabrication process node, the faster the circuit can operate. The faster the circuits, the more significant are the package parasitic capacitances and inductances.

One of the challenges for this forward-looking project was using today's DRAM die to prove out the electrical superiority of a package intended to be used with tomorrow's much faster DRAM ICs, such as DDR4. The DDR4 DRAMs are projected to operate at least up to 3200MT/s over their production lifetime and may reach significantly beyond. By contrast, the fastest DDR3 devices in production today are limited to operation of 2133MT/sec.

Generally, the faster an IC switches, the greater the power bus di/dt. Faster DRAMs are therefore more sensitive to the power supply inductance in the IC package. The aggressively scaled process technology expected to be the mainstay of DDR4 is likely to require a reduction of the operating voltage below the 1.5V used for today's mainstream DDR3 devices. That voltage reduction is expected to aggravate the circuit's tolerance of on-chip power bus noise.

I/O pin transition times must also shrink in order to scale conventional signaling technology from 1600MT/s to 3200MT/s. Reduced I/O switching times usually mean a greater susceptibility to signal integrity issues arising from impedance discontinuities in the signaling path.

The semiconductor package is of keen interest because all signal and power routing to the IC must pass through the package. Because this work was focused on improving these package parasitics and demonstrating it by using live die, the fastest possible die were desired. Additionally, access to the fastest automatic test equipment (ATE) able to operate the devices up to the point of failure while maintaining the best timing resolution was needed.

Using nominal 1600MT/s DDR3 die operated with 1600MT/s timing sets, the experimental legs with employed reference planes constructed from metal coupons showed an improvement of the data eye width. The grounded coupon performed the best, demonstrating a 9.2% improvement while the floating top plane demonstrated a 6.2% improvement vs. the control. Because the Vss connections for the top die were routed through the copper coupon, the Vss inductance was reduced vs. the control.

Conclusion

Three variants of an opposing face DRAM dual-die package were developed and compared using live die on production ATE. The use of a copper reference plane below the bond wires of the upper die was found to improve the data eye width by 9.2% vs. the conventional DDP device.

While this improvement is significant, higher performance DRAM, such as DDR4, is likely to show a greater benefit from this new approach because of the higher switching speed of the DRAM's I/Os and the expected higher di/dt of its power profile.

References

  1. R. Kho, et al., "A 75nm 7Gb/s/pin 1Gb GDDR5 Graphics Memory Device with Bandwidth Improvement Techniques," presented at ISSCC2009, San Francisco, California (Feb. 2009).
  2. U. Kang, "An 8Gb 3D DDR3 DRAM using Through-Silicon-Via Technology," presented at ISSCC2009, San Francisco, California (Feb. 2009).
  3. R. D. Crisp, "Experimental Investigation of the Performance of DDR3 DRAM Packages," presented at ISMP2010, Seoul, Korea (Oct. 2010).

Contact author

Richard Crisp, Fellow, Packaging Division Technology and Thermal Cooling, Tessera Inc. 3025 Orchard Parkway, San Jose, Ca. 95134 USA; ph.:+1 408 219 1820, email: [email protected].

Solid State Technology, Volume 54, Issue 7, July 2011

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