SEMATECH, SIA, SRC pursuing 3D standards - Advanced Packaging
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SEMATECH, SIA, SRC pursuing 3D standards

December 14, 2010 - SEMATECH, the SIA, and SRC have established a new 3D Enablement program targeting standards in inspection, metrology, microbumping, bonding, and thin wafer and die handling.

The project, to be administrated by SEMATECH's 3D Interconnect program out of the U. of Albany's College of Nanoscale Science and Engineering (CNSE) and involving a group of existing member companies, aims to solve a key problem in 3D ICs: no uniform standards and limited understanding of key manufacturing parameters, which would identify the most promising and cost-effective options to be transitioned to mainstream high-volume production.

Efforts will focus primarily on developing technologies and specifications necessary to establish standards in several critical areas: inspection, metrology, microbumping, bonding, and thin wafer and die handling. SRC is being brought into the effort to help enable university research projects, notably in the bonding process and 3D inspection areas. First phase of the project will focus on developing necessary standards and technical specs for 3D ICs, followed by identifying key areas for developing design tools to support 3D chip design. IDMs, fab-lite and fabless companies, outsourced assembly/test (OSAT) suppliers, and tool vendors are all welcomed to participate.

The industry is now at an "inflection point" in 3D integration -- but still faces challenges associated with a lack of standardization, something that requires deep collaboration among the key industry bodies, noted Dr. John E. Kelly III, SVP and director of research at IBM and chair of SIA's technology steering committee. A lack of convergence will delay 3D IC adoption, added SRC president/CEO Larry Sumney; combining SRC's university programs and expertise with SEMATECH's existing 3D efforts will let everyone "an ambitious interface standardization for 3D integration to enable the commercialization of 3D ICs," he said.