Park Systems sponsors SST webinar on metrology challenges and opportunities for semiconductor market

Park Systems is sponsoring a webinar entitled Metrology Challenges and Opportunities presented by  Solid State Technology Magazine on April 14, 2016 at 10am PST. The webinar will address advanced materials used in semiconductor silicon wafer manufacturing and new device structures and designs under various stages of development. The presenter for the webinar is industry expert and SPIE Fellow, Dr. Alain Diebold, whose career includes cutting edge research on advanced metrology methods to improve nanoelectronics fabrication as Director of the Center for Nanoscale Metrology at CNSE.

According to the World Semiconductor Trade Statistics, the worldwide semiconductor market is forecasted to be up 0.3% to US$336 billion in 2016 and up another 3.1% to US$347 billion in 2017. Since 2007, Park has gained a reputation as the technology leader of nanoscale measurement and systems in both research and industry for the semiconductor and other industries and their impressive client list includes HarvardStanfordNASA, NIST, Micron, Imec, Seagate, Western Digital and IBM.

Park Systems provides the best quality AFM for Semiconductor microscopy for failure analysis and defect review, an integral part of the process of advancing semiconductor research and manufacturing. Park Smart ADR is the most advanced defect review solution available, featuring automatic target positioning without the need for labor intensive reference marks that often damage the sample. The Smart ADR process improves productivity by up to 1,000% compared to traditional defect review methods and offers up to 20x longer tip life thanks to Park’s groundbreaking True Non-Contact Mode AFM technology.

“AFM enables the determination of surface and sidewall roughness and feature line shape and is often used in conjunction with TEM, CD-SEM, and Scatterometry in Hybrid Metrology. The goal of Hybrid Metrology is to use the measurement information from multiple methods to improve 3D determination of feature shape and dimensions,” explains Dr. Alain Diebold, Interim Dean at the College of Nanoscale Sciences and Director of the SRC NRI INDEX Center.
Many of the new design challenges and opportunities will be presented in the webinar, showcasing the enhanced concepts under research and being commercialized. A critical role in the development and ongoing application of new device structures and materials is the advanced microscopy provided by world-leading Park Systems Atomic Force Microscopes, designed to meet the industry’s strict requirements for nanoscale accuracy.

“Our AFM technology is still unbeatable because of the high degree of accuracy and repeatability the non contact mode provides and because it is the only wafer fab AFM with automatic defect review,” stated Keibock Lee, Park Systems President. “Park’s fully automated Automatic Defect Review (ADR), designed specifically for the semiconductor industry, is the most advanced defect review systems available, providing identification and enabling a critical inline process to classify defect types and source their origin through high resolution 3D imaging.”

Much emphasis is being placed on new designs for more complex device structures and exploration of highly advanced new materials. This webinar will focus on some of the new device structures such as FinFETs and 3D stacking, new materials that are emerging and how they are proceeding towards future manufacturing. The industry continues to search for materials for transistors and interconnects. For example, a high dielectric constant “high K” material that is compatible with Ge channels are key to enabling the use of Ge channels. Thinner barrier layers for copper interconnects are another topic of research as well as the often mentioned replacement for copper itself.

“Lithography continues to drive a significant research effort. Quadruple patterning will replace double patterning. Double patterning (Self Aligned Double Patterning) refers to the use of oxide spacers on the side of lithographically patterned lines to double to line pattern density,” explains Dr. Diebold. “The space process can be applied multiple times. When the spacer process is applied twice, the pattern density is quadrupled. There are many variations of the use of multi-pattern methods.”

“Over the past several years, the industry has also investigated Directed Self Assembly of Block Co-Polymers as a means of increasing pattern density beyond that possible with traditional lithography. Research into EUV lithography also continues to be a critical topic,” adds Diebold.

Park NX-Wafer makes accurate, repeatable, and reproducible sub-Angstrom roughness measurements for the flattest substrates and wafers with minimized tip-to-tip variation. Park NX-Wafer delivers the industry’s lowest noise floor of less than 0.5 Å throughout the wafer area, combined with True Non-Contact Mode to achieve reliable measurements even for the long-range waviness measurement of scan sizes up to 100m x 100m.


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