IEDM preview: Multi-threshold-voltage Flexibility in FDSOI

IEDM Previews:
Intel fabs highest mobility pFET with Ge channel
University of Tokyo first to demo III-V self-aligned source/drain
IBM, Macronix identify phase-change memory failure mode
Record photodiode quantum efficiency from Taiwan lab
How strain can protect devices from ESD
SEMATECH tipping III-V MOSFET, FinFET, and resistive RAM
TSMC anneal for gate-last HKMG process
Imec IEDM presentations to cover More than Moore, ITRS
When do TSV stresses affect device operation?
Multi-threshold-voltage flexibility in FDSOI
CMOS imager works from light to night
Carbon nanotube vias approach production densities
IBM Alliance simplifies pFET HKMG
IM Flash details 25nm NAND

by Laura Peters, contributing editor

October 27, 2010 - The theme of the upcoming International Electron Devices Meeting (IEDM, 12/6-8 in San Francisco, CA) is finding better ways to generate, transmit, use and save energy. One method of reducing power consumption is by optimizing devices for low power and multi-threshold voltage (Vt) operation. At the conference, a group of researchers will demonstrate low-Vt nMOS and pMOS workfunction-adjusted devices manufactured using TiN/TaAlN metal gates in ultrathin fully-depleted silicon-on-insulator (FDSOI) substrates. The researchers, from CEA-Leti Minatec (Grenoble, France), STMicroelectronics (Crolles, France), AIXTRON AG (Herzogenrath, Germany) and Soitec (Bernin, France), used ground planes under the SOI to expand the Vt capability and body bias boosts for power management. Transistor and SRAM bit cell testing showed neither the gate engineering nor the substrate introduced threshold voltage variability.

The group used 300mm ultrathin body and buried oxide substrates (SOI = 6nm, BOX = 10nm) with indium (p) or arsenic (n) implants to form the ground planes. For the low-Vt pMOS device, which is the most difficult to engineer because of flat-band voltage roll-off, various CVD TaAlN stacks were optimized for Al concentration to obtain tuned workfunction above midgap with good mobility and reliability. The TiN metal gate was tuned at 80mV below the midgap for low-Vt nMOS.

Figure 1. CMOS configurations to achieve four threshold voltages with two metal workfunctions and two ground plane types. (Source: CEA-Leti)

The multi-Vt scheme provides two Vtn and two Vtp devices in four CMOS device configurations (Figure 1) using ground planes of the same type (Vt = 0.32-0.6V). Low Vts are achieved for TiN nMOS and TaAlN/TaN pMOS and vice-versa for high-Vts (Figure 2). The pMOS devices performed at Ion = 500μA/μm and Ieff = 245μA/μm at Ioff = 2nA/μm and Vdd = 0.9V. The researchers point out that the architecture is compatible with power management techniques such as reverse and forward back biasing for each threshold voltage configuration.
This work follows on from CEA-Leti’s announcement earlier this month that it has made available its 20nm FDSOI process to the design community, including high-k/metal gate (HKMG) processes.

Figure 2. Multiple threshold voltages result from the combinations shown in Figure 1. (Source: CEA-Leti)


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