IFTLE 103 2012 IMAPS AZ Device Pkging Conf; Fujitsu Low Temp Cu-Cu Bonding

By Garrou
It's been over for a few months now, but IMAPS was a bit slow this year gathering the presentations from their device packaging conference, This is however understandable and excusable due to the untimely death of IMAPS employee Jackie Joyner. So let's begin looking at the 2.5/3D and significant advanced packaging papers.

SSEC Wet Etch for Via Reveal
Laura Mauer of SSEC discussed silicon wafer thinning to reveal Cu TSV. The standard via reveal processis shown below. SSEC contends that a KOH wet etch process can be used for the final Si removal without etching the oxide liner. This can be sealed with oxide/nitride and then CMP'ed to expose the Cu vias.

Wet etch with HF/HNO3 has also been proposed by ASET and shown to have minimal impact on the electrical characteristics of the transistors [link].
Asahi Glass TGV (Through Glass Vias)
Takahashi of AGC discussed the fabrication of TSV in glass. They have been able to fabricate TGV with a  193 nm ArF excimer laser by using short pulse width (20-30 ns). The TGV do have significant slope. Better results are achieved when the glass is processed at elevated temperature ( i.e 200C)

Focused electrical discharge can also be used to process TGV in less than 1 ms. AGC claims that there is no physical limit to TGV diameter using electrical discharge. Electrical discharge TGV show smooth sidewalls and rounded via edges. Similar to the laser process the process requires no masks.

Underfill options - Hitachi, Lord, Dow
Hitachi Chemical discussed non cnductive pastes and films. Packaging in general is moving towards finer pitch and smaller gaps requiring a change in underfill materials and procedures.  NCP and NCF applicable for fine pitch and narrow gaps. In terms of pad finish, Hitachi notes that Cu with OSP "is more difficult to have a good connection."

Lord detailed their screen printable NCP ( Tg = 166 C; Mod = 4.1 Gpa) with built in fluxing agent which allows them to do cu-cu bonding on oxidized cu studs. Similarly Dow presented data on their new pre applied underfill (WUF) films with the following materials properties:

Vacuum lamination is preferred and curing is done at 175C for 1 hr. Voiding seen after bonding can be eliminated by pressure curing or optimizing the film thickness. Initial reliability tests indicate good adhesion through MSL-3- 260 C and TCT cond B.

Fujitsu Low Temp Copper-copper Bonding
Fujitsu described further advances in their low temp Cu-Cu bonding technology [link].
Their unique process uses a diamond bit milling machine to achieve a highly uniform and highly polished (7 nm surface vs 210 as plated) which can be thermo-compression bonded at RT and shows grain growth across the interface at 200 - 250C vs 350 C+ for a  standard CMP'ed surface.

Underfill and Cu bumps can be simultaneously cut together by diamond bit with no residue on bump, but hybrid copper/underfill interface exposed to formic acid before bonding "could not sustain arranged location during bonding process." However, if the interface is bonded first and then exposed to formic acid, "partially exposed," clearly grain growth occurs as low as 140 C.

For all the latest on 2.5/3D IC and advanced packaging stay linked to IFTLE.........................

Dr. Phil Garrou gives his insight into leading edge developments in 3-D integration and advanced packaging, reporting the latest technical goings on from conferences, conversations, and more.

Previous Posts

IFTLE 116: A6 applications processor for iPhone 5 from Samsung, but...


IFTLE 115: No nickels; SCP quals low-volume TSV manufacturing; 3D IC slowdown; Apple/TSMC timetable


IFTLE 114: 28nm capacity nickels, and a "symbiotic relationship"


IFTLE 113 An Exclusive Interview with Mr Lester Lightbulb


IFTLE 112 TSMC Staffing up for 2.5/3D Expansion ; Semi 3D Standards; Sony shows off 3D stacked Image Sensors


IFTLE 111 New Temporary Bonding Technologies Introduced at Suss 3D Workshop


IFTLE 110 Samsung Breaks Wall of Silence at DAC 2012


IFTLE 109 2012 IEEE VLSI Conference ; Lester’s cousin CFL Dies Prematurely


IFTLE 108 2012 ECTC 2: NCF, WUF, MUF for tight pitch Assembly


IFTLE 107 2012 ECTC Part 1 Committees and Awards


IFTLE 106 2012 Symp on Polymers for Microelectronics


IFTLE 105 TSMC Tech Symp; UMC Investment; Latest rumors on IBM, Intel, Samsung and Apple


IFTLE 104 IMAPS DPC Part 2; Over 50% of TI WB Converted to Copper


IFTLE 103 2012 IMAPS AZ Device Pkging Conf; Fujitsu Low Temp Cu-Cu Bonding


IFTLE 102 “3.5D Interposers to someday replace PWBs” - TSMC; GF engaging with 3D customers; Intel predicts Consolidation


© 2012. PennWell Corporation. All Rights Reserved. PRIVACY POLICY | TERMS AND CONDITIONS