AT&S debuted a new technology to enable system-in-package (SiP) devices. AT&S’s embedded component packaging technology ECP is used to enable further miniaturiztion of electronic devices while enhancing their performance.
Package-on-package, implemented with flip chip package assembly, is meeting requirements for next-gen mobile devices. Challenges remain: fine pitch underfill, brittleness of ultra low-k (ULK) dielectrics, and shorting between adjacent bumps. Craig Mitchell, Tessera, examines the lucrative 3D packaging step and how to face these challenges.
Advanced Packaging asked our readers where -- at the foundry, in a dedicated semiconductor assembly and test services (SATS) house, or on the SMT line -- package-on-package (POP) assembly should take place.
Tessera Technologies (Nasdaq:TSRA) announced that Bruce McWilliams, PhD, has resigned as a member of Tessera’s board of directors effective immediately, to devote his time and attention to the needs of SuVolta's growing business.
Brush Engineered Materials Inc. (NYSE:BW) will change its name to Materion Corporation (NYSE:MTRN) and unify all of its businesses under the new name effective March 8, 2011.
Dr. Phil Garrou looks ahead to a laundry list of changes coming in the next ITRS Update with respect to assembly and advanced packaging, including 3D integration, interposers, and applications from medical to automotive and embedded applications.
STATS ChipPAC Ltd. (SGX-ST:STATSChP), semiconductor test and advanced packaging service provider, expanded its wafer level package (WLP) offering with new 300mm manufacturing capabilities in Taiwan.
CEA-Leti is expanding its technology offering, ramping up one of Europe’s first 300mm lines dedicated to 3D-integration applications. The new line is dedicated to R&D and prototyping and includes 3D-oriented lithography, deep etching, dielectric deposition, metallization, wet etching, and packaging tools.
The Role of Wafer Bonding in 3D Integration and Packaging
There are numerous process integration schemes currently in place for the implementation of 3D-IC. Via first, via middle, via last along with back end of line (BEOL), ...
Sponsored By: Suss MicroTec
RoHS Means Big Changes for Power Devices. Are you Ready?
While design and assembly of today’s smaller, higher functioning semiconductor devices continues to be challenging, addressing the thermal requirements of ...
New Die Attach Film Raises the Bar on Wetting and Molding Performance
Complexity, functionality, miniaturization and cost-efficiency have been and continue tobe the mantra of the electronics industry. Arguably, no segment is more keenly ...
New Wafer Backside Coating Innovation Stacks Up Against Film
Consumers continue to drive demand for smaller, thinner and more capable electronicdevices which, then, require integrated packages that can cope with today’s ...
µPILR Flip Chip for High-Performance Applications
The ever increasing market requirements for high-performance, high speed, and densely packaged devices with shrinking form factors have propelled the use of flip ...
Sponsored By: Tessera Technologies, Inc.