Insights From Leading Edge

IFTLE 22 Sources for Fanout WLP Continue to expand

FO-WLP (Fan-Out Wafer Level Package) is the general term for a type of package that employs wafer-level redistribution technology and supports formation of redistribution layers outside the chip area. FO-WLP has been discussed numerous times [ see Solid State Technology, “Highlights from the ECTC”, 06/15/2010; PFTLE 72, "The Samsung Roadmap That Isn't", 04/16/2009] .The first 200 mm FO-WLP wafers were mass produced at Infineon, STATS ChipPAC and ASE in 2009. It is quite apparent from its successful introductions that it is becoming the next BGA in terms of package popularity.

Current FO-WLP practitioners include licensees of the Infineon e-WLB [embedded wafer level BGA] including ST Micro, ASE, STATSChipPAC and Nanium (Qimonda Portugal) and Nepes which has licensed the Freescale RCP [redistributed chip package] technology which is similar.. Amkor and others are known to have similar products in development.

The 2010 marketplace for FO-WLP, as determined by Yole Development, is shown below.

At the September IEEE ESTC meeting in Munich, Renesas announced their entry into the FO-WLP club. Recall that the new Renesas is a merge of Renesas and NEC which began combined operations in April 2010 [link].

Their technology will first be used in microcontroller (MCU) products, which require small chip size and high interconnect density. Their listed specs include: interconnect density (L/S = 15/10 μm, interlayer via pitch = 50 μm); chip size (5 mm �? 5 mm or less) and thickness (0.3 mm) package.

The process flow involves following steps: (1) Photo PI is deposited on a Si support wafer and the patterned; (2) Cu RDL is deposited and patterned using a semiadditive process; ( design rules for Cu wiring were 15 μm in width, 10 μm in space, and 5 μm in thickness); (3) Cu pillar bumps (CPB) with Sn-Ag solder caps were formed at relevant positions on the top Cu wirings; (4) IC chips were separately prepared with electroless Ni/Pd/Au plating on I/O pads; (5) chips attached by die-to-wafer bonding; (6) MUF (molded underfill) of the chip-bonded RDLs on the support wafer; (7) The Si support wafer was removed from the chip-bonded RDLs to form a chip-embedded resin wafer with RDLs; (8) The wafer was diced and separated into an individual packages (Before dicing, additional metallization for external terminals such as Au plating, solder ball mounting, or solder paste printing occurs).

Below we see a 1.6-mm square 8-bit microcontroller chips with the 75-μm-pitch I/O pads were assembled in a 2.0 mm x 2.0 mm FO-WLP with 2-metal fan-out RDLs. A cross-section and images of the prototype are shown in Fig. This package is a 80% reduction vs previous pkg size.

Multiple chips can be encapsulated in the same package (SiWLPâ??¢ [system in WLP]) such as the MCU and analog Rf chip shown below.
Such packages reportedly pass 1000 cycles of -40 to + 125 temp cycling. Dr. Kurita indicated that such MCU packages would be in volume production by 2012.

Next Week: Xilinx rumors prove correct, info from the IMAPS National in Raleigh.

For all the latest in 3D IC integration and advanced packaging stay linked to Insights from the Leading Edgeâ??¦.


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