Insights From Leading Edge

IFTLE 27 Era of 3D IC Has Arrived with Samsung Commercial Announcement

Back in Nov 2008 PFTLE called on Mick Jagger and “Mr Jimmy” to explain why we “don’t always get what we want". What we wanted two years ago were commercial announcements, from someone, from anyone using 3D IC technology. [ see PFTLE 53, “You Can’t always Get what You Want”] While there were no blockbuster announcements that week in the fall of 2008 we did get assurances that the industry was steadily, if not rapidly, moving forward and that we are not wasting our time or money chasing this technology (or at least we hoped so).

Well, we often hear that “all things come to those who wait” and indeed this past week for those of us who are 3D prognosticators, our dreams have come true. Not that there was any reason to doubt after the Elpida,UMC, Powertech partnership announcements of this past summer, but I’m sure lots of 3D enthusiasts broke out the champagne this week after the announcement by Samsung. Both the Elpida and Samsung announcements contain all (3) requirements for full 3DIC; i.e thinning, stacking and TSV.

Similarly, this weeks IBM announcement following the Xilinx /TSMC/Amkor announcement a few weeks ago [ see IFTLE 23, “ Xilinx 28 nm Multidie FPGAâ??¦” ] gives added credibility to the commercial viability of high density interposers with TSV for advanced packaging solutions. With multiple announcements in each category now “under our belts” IFTLE proudly announces that the Era of 3DIC has arrived.

As was the case with image sensors [ see PFTLE 46, “…..on Mechanical Bulls, Rollercoasters and CIS with TSV” ] we can expect other memory producers to follow with announcements or eventually loose market share. Will Hynix or Micron announce next ?

Samsung Memory Stack

On Dec 7th Samsung announced that it “â??¦has begun mass production of 8GB DDR3 memory modules based on the SODIMM form-factor used by many notebooks and mobile workstations”. The modules are based on four-gigabit, 1.5V, 40 nm DDR3 memory chips operating at 1,333MHz and 3D TSV chip stacking technology. A single 8GB DDR3 module using the new technology is claimed to offer a 53% power savings compared to two 4GB DDR3 modules, and a 67 percent power savings compared to 1.8V DDR2 components. Samsung announced plans to apply the higher performance and lower power features of this TSV technology to 30nm-class and finer process nodes. This is only a two chip stack, but it is the beginning.
The modules are purposed for use in high performance servers where its TSV technology is a key to lower power consumption while increasing memory capacity and improving performance. Adoption is expected starting in 2012. The modules will be available as an option in Dell’s Precision M6500 mobile workstation, which will fill four slots totaling 32GB of memory. There was no indication of pricing or price comparison to non 3D components.

IBM 3D Interposer

The following day, IBM and Semtech announced that Semtech will use IBMs 3D TSV technology to develop a high-performance ADC/DSP platform for “â??¦ fiber optic telecommunications, high performance RF sampling and filtering, test equipment and instrumentation, and sub-array processing for phased array radar systems”.

Calling the technology a “â??¦ first-generation 3D multi-chip module” Semtech will utilize IBM’s 300 mm 3D interposer technology to interconnect ADC functions in IBM custom logic (SOI-based Cu-45HP technology) with interleaver ICs (IBM’s 8HP BiCMOS SiGe technology). The disparate technologies are connected through a single 90 nm wiring layer on a 3D interposer, which supports a bandwidth of greater than 1.3 Tbps in this design.

Ultra high density capacitance is provided by integrating deep-trench (DT) capacitors at the top surface of the interposer. The interposer connects to the next level package with copper TSV technology. The figure below shows SEM cross sections of the interposer chip and deep trench capacitors.

IBM will provide semiconductor fabrication, wafer finishing and assembly for Semtech. Integration of data converters with DSPs reportedly has been a difficult problem due to mixed IC technology requirements and lack of high power, high bandwidth interconnect. The 3D technology allows integration of the CMOS and SiGe technology at very high bandwidth and with low power to provide a high-performance module solution.

Semtech will have first ADC/DSP prototype modules available in 2011. Near-term applications include 100 Gbps coherent receiver for fiber optic telecommunications, high performance RF sampling and filtering, test equipment and instrumentation, and sub-array processing for phased array radar systems.

GSA Creates 3D Integrated Circuit (IC) Initiative

The GSA (Global Semiconductor Alliance ) has announced a new 3D IC Initiative. The GSA’s goal is to help accelerate an industry-wide transition to make 3D IC technically feasable, as well as cost-effective, for a wide range of applications and increase ROI for early adopters.

Part of the 3D IC initiative includes the formation of the 3D IC Working Group which will include participants from the major semiconductor companies, the supply chain including EDA, packaging and foundry. The GSA hopes to continue to work with other interested organizations on standards and other synergies to drive economies of scale and therefore has initiated relationships with IMEC, ITRI, SEMI , SEMATECH and Si2 to help in such efforts.

The GSA will hosts its second annual Memory Conference on March 31, 2011 in San Jose. The theme for the 2011 conference will be Memory and Logic Integration and the Benefits of 3D IC Technology.

SEMATECH /SIA /SRC Initiate 3D Enablement Program

SEMATECH, the SIA (Semiconductor Industry Association) and the SRC (Semiconductor Research Corporation) have established a “3D enablement program” to drive industry standardization efforts and technical specifications for 3D heterogeneous integration.

The new 3D program, launched by a group of existing member companies in SIA and SEMATECH, will focus primarily on developing technologies and specifications necessary for establishing standards in critical areas such as inspection, metrology, microbumping, bonding and thin wafer and die handling. To achieve this, SEMATECH will partner with SRC to enable select university research projects. The program will address these industry infrastructure gaps in phases. First efforts will focus on developing the necessary standards and technical specifications, followed by planning activities to identify the key areas for developing design tools to support 3D chip design.

The 3D Enablement program is open to international fabless, fab-lite and IDM companies, outsourced assembly and test (OSAT) suppliers, and tool vendors.

Coming up next;

â??¦..IEEE 3D Test Workshop
.â??¦.IEEE 3DIC Conference
â??¦..RTI 3D-ASIP

For all the latest in 3DIC and advanced packaging stay linked to Insights From the Leading Edgeâ??¦.


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