Insights From Leading Edge

IFTLE 68 2011 Semicon Taiwan SiP Global Summit Part 2. 3DIC Technology and Test

The SiP global summit was held recently in Taipai. Last week we looked at the some of the 3D technology forum. This week we will finish up on 3D technology and look at highlights of the 3D Test forum "Test Challenges and Solution in the New Era of Heterogeneous Integration," chaired by Mike Liang, president and CEO of KYEC. Multiple Packaging and Testing challenges must be met to meet the production yields required to take 3D from concept to commercialization. It is crucial that the entire supply chain of material suppliers, design houses, test equipment suppliers, and package and testing houses partner to develop cost-effective test mythologies and strategies.

Victor Peng, SVP at Xilinx, updated the audience on their ongoing commercialization of Xilinx 7V2000T FPGA with their "stacked silicon interconnect technology" (SSIT).The company’s FPGA 28nm slices are assembled "side by side" on a silicon interposer with 65nm interconnect wiring. They found the interposer was an excellent way to handle the 28nm chip low-k fragility.Chip fabrication, interposer fabrication and bumping is being done by TSMC. Chip bumping and module assembly is being done by Amkor.

Peng reports that Xilinx is on schedule for sampling in calendar year 2011. Peng also noted that the company "believes in full 3D IC stacking (no interposer)" but that it will take a little longer for that technology to become standardized in the infrastructure.

Recall in IFTLE 62 I discussed the nomenclature confusion part of which was "stereoscopic 3D" being confused with 3D IC. [ see IFTLE 62, "3D and interposers: Nomenclature confusion"] Well, I never thought I would see a presentation about 3D IC being used for stereoscopic 3D but that’s just what happened when Taiji Utaka, SVP of technology platforms at Sony discussed the incorporation of 3D IC chips into the stereoscopic 3D Sony PlayStation. Sony is looking at the potential of improving 3D image quality by using 3D IC memory to increase performance (pixel fill rate improved by higher bandwidth) and improve latency. Sony sees the major impediment to using 3D IC as current cost, but also includes test protocol, thermal performance, proven reliability, standardization, and the availability of multiple suppliers as issues that need to be improved. Utaka interestingly noted that "game machines are required to have longer lifetime than PCs."

Jim Walker, VP of semiconductor Manufacturing for Gartner during his presentation "Going Vertical" looked at "register DIMM" used in servers comparing the newly announced Samsung 32Gb DDR3 DIMM with through-silicon vias (TSV) to previous 32Gb RDIMM. He finds the TSV-based products operate at lower power and higher speed:

— Lower power: 4.5 Watts = 30% less than current 32Gb RDIMM without TSV
— Higher Speed: 1333 Mbit/sec vs. 800 Mbit/sec previous 32Gb RDIMM

Eric Beyne of IMEC sees the current market divided into the following segments:

Mobile consumer applications

Memory/logic stacks:
- Increased memory bandwidth, low power
- Analog-logic stacks: Heterogeneous technology choices

High-performance applications:
- Very high memory bandwidth requirement
- Very high power processor devices
    3D SI interposer substrates

High density memory stacks:
- High bandwidth, low power DRAM

Microsystem integration:
- Combining advanced logic and memory technologies with heterogeneous device technologies such as analog, sensor, actuator, MEMS

Beyne concludes that it is difficult for designers to actually use the technology due to too many unknowns, and lack of 3D-EDA. The numerous technology options create a complex supply chain and make it difficult for equipment, material and EDA tool suppliers to develop the appropriate solutions. Thus, Beyne indicates that standardization is needed immediately in: 3D technology, 3D test, and 3D design.

Roger Hwang, director of test at ASE, noted that test must be built into the 3D TSV assembly flow at the OSAT.

At ASE, logic die will be tested after being mounted onto the substrate "strip" before singulation, and memory will be tested after tape and reel. Another test will be done to the final package after chip-to-chip bonding.

Interposer test will be done after backside processing and after film frame mounting.

Greg Smith of Teradyne listed the following unique TSV fault types:

Faults can occur in the TSV itself:

  • Voids (High resistance)
  • Oxide pinholes (short to substrate)

Faults can occur from bonding:

  • Contamination of bond surface
  • Misalignment
  • Height variation
  • TSV shorts

Faults can occur from wafer thinning:

  • I-V degradation
  • Shifts in device performance

For all the latest in 3D IC and advanced packaging stay linked to IFTLE………


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