This yearâ€™s Design, Automation and Test Europe Conference [DATE] was held in Dresden. This yearâ€™s 1 day 3D Integration workshop was headed up by Sandeep K. Goel (TSMC), Qiang Xu (Univ Hong Kong) and Saqib Khursheed (University of Southampton).
ARM, IMEC and the Swiss Federal Institute of Technology (EPFL) gave an interesting presentation on the "Performance and Efficiency of 3D Stacked DRAM in a Multicore System." The goal of this 2010 - 2012 European commission funded project, known as "Euro Cloud," is to integrate ARM processor cores with 3D DRAM for very dense, low power data centers for mobile cloud services for hand held devices. Coupling of high performance ARM Cortex processors with 3D memory is targeting the mobile cloud services from Nokia which will serve millions of "mobile handsets." Their analysis shows that although 3D-stacked DRAM, such as Wide-IO, allow for wider buses by providing increased pin density, the wider buses saturate in providing additional throughput. The authors propose that rather than increasing the width, more channels that are effectively managed by memory controllers lead to increased overall system performance. They also conclude that 2.5D is preferable to 3D for systems with challenging thermal performance.
(Click on any of the images below to enlarge them)
Hsien-Hsin Lee of Georgia Tech presented more details on their 3D MAPS massively parallel processor with stacked memory [we have discussed this previously in IFTLE 93, "2.5 / 3D at the 2012 IEEE ISSCC"]
Of interest were their designs for V2 which will have 5 layers and a wide IO interface. It is shown schematically below with proposed specs compared to 3D MAPS 1
The Fraunhofer ASSID group presented their thoughts on quality inspection strategies for 3D chip processes. Their concept is that I line metrology is needed to save time and materials.
TSV metrology tasks include : determination of uniform TSV depth; barrier and seed defects and voids during TSV filling and determination of bump height and coplanarity in copper pillar bump interconnect.
Synopsis unveils its 3DIC EDA solution
Synopsys recently unveiled its comprehensive EDA solution, including enhanced versions of its IC implementation and circuit simulation products.
Synopsys reports that they are delivering a comprehensive EDA solution including :
-DFTMAX: design-for-test for stacked die and TSV
-DesignWare STAR Memory System: integrated memory test, diagnostic and repair solution
-IC Compiler: place-and-route support, including TSV, microbump, silicon interposer redistribution layer (RDL) and signal routing, power mesh creation and interconnect checks
-StarRC Ultra: parasitic extraction support for TSV, microbump, interposer RDL and signal routing metal
-HSPICE and CustomSim circuit simulation: multi-die interconnect analysis
-PrimeRail: IR-drop and EM analysis
-IC Validator: DRC for microbumps and TSVs, LVS connectivity checking between stacked die
-Galaxy Custom Designer: specialized custom edits to silicon interposer RDL, signal routing and power mesh
-Sentaurus Interconnect: thermo-mechanical stress analysis to evaluate the impact of TSVs and microbumps used in multi-die stacks
The Synopsys 3D-IC solution is expected to be in production in calendar Q2 of 2012.
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