Insights From Leading Edge

IFTLE 151 2013 IMAPS Device Packaging Conf part 1 - Amkor

I’ll be interspersing reports from DPC with ECTC and ICEP reports so pay attention as to where the material over the summer is coming from. In addition I will be covering ConFab and Semicon West so there will be a lot of information coming your way.

The IMAPS DPC , Proceedings and the Literature Search Problem

We are finally getting around to taking a look at the March IMAPS  Device Pkging Conference. Actually it is officially listed as a workshop, which to IFTLE is inappropriate since it runs 3 parallel sessions for 2 ½ days and has a very large exhibit tied to it. It seems the driving force to not change is that SOME don’t want to write up their papers for a proceedings which would be required if it were officially a conference. These are probably the same authors who don’t ever hand in, or take 2+ months to turn in , their slides. When I was general chair I tried twice to require a proceedings and was voted down twice, so don’t blame me !

In the end its all about literature searching. We all have become so accustomed to using Google scholar that if it doesn’t show up there we just ignore it. If I don’t have a copy of a specific proceedings and its papers don’t show up in Google Scholar basically the material does not exist. Sure I can go to each societies web page, and become a member and then search their archives but how many of us do ? Right now that means we all reference quite a bit of literature from IEEE explore because Google indexes it and our companies / institutions pay to access it.

Other societies need to make sure their material is archival and searchable otherwise after a few years it is really lost. I know IMAPS specifically is working on this problem and I hope all the other societies are too.


Lets start our DPC look with presentations from Amkor. Being close by in AZ, Amkor always brings a strong contingent to the DPC.

Amkor discussed their thermo compression non conductive paste process for formation of copper pillar bumps. Copper pillar bumping achieves better electrical performance as well as smaller packages with lower standoff heights. It is also expected to lower costs by reducing substrate layer counts. The bump process flow is shown below:

The assembly process for thermocompression bonding with non conductive paste (TCNCP) is shown below. Key to the assembly process is control of the peak heating temp and the heating time.

Amkor also discussed mold shrinkage and die stress effects on FC molded BGAs.
FCBGA can be molded using either mold compound or molded underfill. Schematic of molding is sown below. Increased shrinkage increases both  tensile and shear stresses.
Stresses are concentrated in the mold/ die interface in the mid section of the die.  The rubber insert used to protect the die surface creates a grove in the top of the molded surface. This grove controls the stress on the overall package and this package warpage.

Kelly of Amkor  discussed “Assembly challenges for 2.5D”. Their latest roadmap now shows memory + logic modules pushed back to the 2014 – 2015 timeframe.

Their TSV manufacturing experience base is based on :

High performance products now look like they are coming in 2014 – 2015 with smart phone % tablets coming in 2015+ as prices come down
Amkor has been engaged with > 10 top tier customers with > 20K parts built. There has been a  large package  focus (> 40mm) . While the slides showed interposers from 3 different “foundries” upon questioning they admitted that TSMC is delivering and the other two (Global and UMC) are close.
Process technology
- Their copper pillar bump process is on 40-45um for most customers roadmaps.
- for die joining  mass reflow is preferred but warpage must be well under control. TC bonding is an option for higher die warpage.  TCNCP can be used for small die and CUF for larger die.
- backside passivation must be mechanically stable, good adhesion to underfill and provide warpage control. In the Q&A session they indicated that they preferred inorganic backside dielectric “â??¦sometimes with a final organic cap” indicating that the “â??¦backside oxide must be incredibly mechanically robust. “
- Interposer top side to bottom side die interfaces must be flat in order to assemble.
- Need to know top side stress on incoming wafers in order to properly assemble.
- memory stacks are pretested
Comparison of 3 assembly flows is given below

For all the latest in 3DIC and advanced packaging stay linked to IFTLEâ??¦â??¦â??¦â??¦â??¦â??¦â??¦â??¦


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