Insights From Leading Edge

IFTLE 167 IARPA Trusted Integrated Chips program (TIC); The Apple A7


In the US, we are approaching Oct 31, the day for pumpkins and witches. Hannah and Madeline wish all IFTLE readers a Happy Halloween.

H and M

IARPA Trusted Integrated Chips

At the IEEE 3DIC in San Francisco Dan Radack of IDA [Institute of Defense Analysis] recently gave an update on the  IARPA trusted Integrated Chip Program known as TIC


From 19996 – 2006 the IC Fab at Ft Meade was used to fabricate ICs required for Govt. programs. It was mothballed 5-6 years ago. From 2003 to present the Govt. has used so called “trusted foundries” but they found that they were not able to provide everything that the Govt. needed.

With all of the top foundries now situated outside the US or owned by non US entities, there was a need for a new way of ensuring secure state of the art chip procurement. This certainly dovetailed with the interest in cyber security i.e. how to prevent counterfeits and the vision of needing more-than-Moore technology (i.e. sensors in a 3D chip stack) in the future.

Trusted Integrated Chips program TIC

In the summer of 2011 The Intelligence Advanced Research Projects Activity (IARPA) announced its  Trusted Integrated Chips program. TIC features what IARPA calls “split-manufacturing,” where fabrication of new chips is divided into Front-End-of-Line (FEOL) manufacturing consisting of transistor layers to be fabricated by offshore state-of-the-art” foundries lines and Back-End-of-Line (BEOL) development that would be fabricated by trusted U.S. facilities.

In this approach, the design intention is not disclosed to the FEOL fabricators. “FEOL circuit fabrication to the point of only the first metallization layer can be used to obfuscate the design and performance of an integrated chip thereby protecting the intellectual property of the designer. Alternately, circuit obfuscation can be realized through a chip integration strategy whereby only partial circuits are fabricated on any single chip but when integrated with other chips or wafers in a US manufacturing or packaging facility, a complete safe and secure circuit or system can be realized,” IARPA stated.

According to IARPA, the vision of the TIC Program is to ensure that the United States can:

• obtain the highest performance possible in integrated circuits;

• obtain near 100% assurance that designs are safe and secure — not compromised with malicious circuitry;

• ensure security of designs, capability, and performance while simultaneously protecting intellectual property; and

• realize secure systems combining advanced CMOS with other high value chips.

The TIC program is examining  a number of split-manufacturing concepts in the following areas:

• Mixed Signal                       • Photonics-CMOS                       • MEMS-CMOS

• Power-CMOS                      • RF CMOS                                  • Memory-CMOS

• Josephson Junctions-CMOS                    • Other systems integrated with CMOS

The five-year program was divided into three phases with the development and demonstration of split-manufacturing starting at the 130 nm technology node in Phase 1. It is anticipated that the TIC Program performers will scale the development of their capabilities to the 22 nm node at the end of a five-year period in Phase 3.

Sandia National Laboratories was selected to coordinate the FEOL and BEOL processing with Multi-Project Wafer runs carried out by the University of Southern California/Information Sciences Institute (USC/ISI) using their MOSIS service.

6 organizations did design of CMOS circuits in the MPW multi project wafer. Global foundries performed the front end work and  IBM Burlington fabricated the interconnect layers. Each of the 6 designers then capped the structure with their heterogeneous layer.

NGAS, Cornell, Lucent, Raytheon Vision systems, CMU, Stanford

Raytheon capped with focal plane array for vision system

Carnegie Mellon – cap with piezoelectric MEMS containing digital, analog and smart SRAM

Bell Labs / Lucent – cap in photonics layer

Northrup Grumman – InP mm wave circuits

Cornell – FPGA with ultrasonic comm. Cap

Stanford - cap with materials and ReRam (resistive RAM)

The program is now moving to 65 nm. The move to 28nm will be June or 2014

Details on the Apple A7

The Apple A7 is a PoP 64-bit SoC designed by Apple.  It first appeared in the iPhone 5S, which was introduced in September 2013. Apple states that it is up to twice as fast and has up to twice the graphics power compared to its predecessor, the Apple A6. The A7 is a 64-bit 1.3GHz dual-core CPU coupled with what’s believed to be a Power VR G6430 GPU. The A7 is manufactured by Samsung on a high-κ metal gate (HKMG) 28 nm process and the chip includes over 1 billion transistors on a die 102 mm2 in size.


Fellow blogger Dick  James from Chipworks has sent the first shots of the PoP processor. He comments that  “”It looks as though there is some degree of bowing in the top package, and there is an interface layer between the two packages. Another surprise is silver wire in the Elpida DRAM package..the pitch of the TMV (through mold via) between the top and bottom packages is 0.35mm. Ball pitch on the base is 0.4mm. There are 3 rows of TMVs for a total of 456. Ball count on the base is 34 x 38 = 1292.”

Cross section of the A7 is shown below.


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2 thoughts on “IFTLE 167 IARPA Trusted Integrated Chips program (TIC); The Apple A7

  1. Dev Gupta

    Phil :
    Are we sure that the Apple A7 PoP package uses TMVs like the A6 and not gone back to solder balls for the vertical interconnect between the 2 levels ? Do take a look at ChipWorks’ teardown report on the iPhone 5s. They have provided a photo of the PoP after pulling off the DRAM pkg. See what you think.

    The other point to note is that the number of vertical interconnects have been increased ( 3 instead of the 2 rows till A6 ) to cater to the 64 - bit wide ( both data and address bus ) architecture of the A7.

  2. Pingback: Blog Review November 5 2013 | Semiconductor Manufacturing & Design Community

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