Insights From Leading Edge

IFTLE 326 2017 SEMI Euro 3D Summit: Thermo-compression Bonding and Plasma Dicing

By Dr. Phil Garrou, Contributing Editor

Continuing our IFTLE look at the 2017 SEMI Euro 3D Summit.


Alistair Attard of Besi discussed “Productivity Improvements in Thermo-compression Bonding (TCB)”.

TCB allows stacking of thin devices at ultrafine pitch ansd as such is an enabling technology for 2.5D and 3DIC stacking. Currently TCB mainly addresses low value high end applications which are performance and form factor driven and have lower cost sensitivity. TCB can be used with non conductive paste, capillary underfill or non conductive films.

Besi 1



- Not well suited for 3D integration (dispensing at each stack layer, NCP bleed, etc.)

- Challenging process for thin dice (< 50μm) due to NCP climbing to the top of the die

- Underfill flow issues for high density fine-pitch bump arrays

- Risk of NCP entrapment in the solder joints


- No issues with adhesive bleed, adhesive entrapment, thin die handling, tool contamination

- Mature CUFs are available

- Proven process for HVM of memory stacks

BUT - Longer process times due to increased process control and solder solidification

- solder joints are not protected until the underfill step – greater risk of joint cracks


- NCF solves some issues of NCP & CUF, but it is still challenging

- Ideal process for thin die & 3D applications

- Reduced die stress due to presence of NCF (good for ULK)

- Shorter process times and collective bonding strategies enable higher UPH

- NCF voiding needs to be controlled

- NCF not yet a mature process

When compared to flip chip mass reflow, TCB is ~ 2X more expensive and is at least 5X slower. In order to be used in larger applications, these issues must be improved upon.

Productivity is increased by reducing the overall TC process time by either of the two approaches shown below (being called Vertical Collective Bonding or VCB):

Besi 2

Besi claims that VCB (gang bond in press) will reduce COO > 5X.

VCB bond profile needs to be optimized (Force, Temp, Timing)

- to get good NCF flow before solder reflow

- to minimize NCF voiding

- to get good soldering at all die levels


SPTS (Orbotech)

Dave Butler of SPTS (now Orbotech) discussed “Plasma Dicing is Becoming Mainstream”.

Conventional dicing includes the following techniques:



Plasma dicing, being offered by SPTS and others uses the same plasma source as DRIE, with the following reported advantages:

No Damage

- Clean, chemically etched scallops

- Active cooling to prevent wafer heating

- Increased die strength

- Yield improvement –no cracking or chipping with plasma dicing

- Advantage for thinner wafers (≤50μm)

Die Density

- Narrow lanes (<10μm) increase usable Si area

- Crack stop areas can be eliminated


- Parallel process

- High Si etch rates –even with more lanes for smaller die

- Option to use cluster platforms

SPTS reports plasma dicing gives ~ 2X die strength vs typical dice after grind techniques.


Reinhard Windemuth of Panasonic also presented info on “Advanced Plasma Dicing”. Pointing out the same advantages as SPTS, Panasonic reports ~ 20% increase in 0.5mm chips from an 200mm wafer due to the reduction in the size of the dicing streets as well as the near elimination of chipping and damage layers as shown below.

panasonic 1

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 325 Omnivision takes Ziptronix License; Semi Europe 3D Summit Part 1

By Dr. Phil Garrou, Contributing Editor

Before we take a look at the recent SEMI European 3D Summit, a little news on the licensing front.

OmniVision Signs License Agreement with Ziptronix

Well, actually Ziptronix as we all know by now was acquired by Invensas, a division of Tessera, in the fall of 2015.[see IFTLE 253 “China Inc Seeks to Acquire GF; Tessera Acquires Ziptronix … “]

But now, Tessera has changed its name (as of Feb 22nd) to Xperi (link).

The key issue here is that Ziptronix owns patents for direct oxide bonding and copper/oxide so called hybrid bonding ( they call tehse technologies Zibond and DBI). This technology that is being used extensively in the CMOS image sensor (CIS) market and was licensed to Sony, the accepted world leaded in CIS in 2011 [link]

There has been ongoing litigation with Omnivision over violation of the Ziptronix patents since 2010. [link]

A few weeks ago that litigation was resolved when Tessera announced that its subsidiary Ziptronix had reached a licensing agreement with OmniVision. In turn, the outstanding litigation by Ziptronix against OmniVision and TSMC has been dismissed.[link]

FYI, the Ziptronix IP has also been licensed by aerospace leaders Raytheon, Teledyne and supplier Novati.

2017 SEMI European 3D Summit

The Annual SEMI European 3D Summit took place in late January in Grenoble France. For the next few weeks we’ll be taking a look at some of the interesting presentations that were given there.

Meyer - Infineon

Thorsten Meyer, one of the early players in FOWLP used a great simple slide to show the advantages of FOWLP over 2.5D interposers for select lower density cases. Basically the FOWLP (like eWLB) can reach the 200um pitch directly without the high cost silicon interposer. When this can generate enough IO for your application, this could be the most economical solution.

Intel 1


Wolf – Fraunhoffer Institutes

Juergen Wolf examined the technologies available in the Fraunhoffer institutes for “Heterogeneous Integration for 3D systems.”

Of interest is their work with Osram and Infineon to develop GaN LED chips n Silicon drivers as shown below.

Wolf 1


Wolf also announced that Fraunhoffer is working with Ziptronix on their DBI bonding technology and showed a 96% yield on DBI test vehicles.

  • DBI is an extension of Ziptronix’ ZiBond technology that allows an interconnect pitch of less than 10-microns, and accommodates 1.5 million connections per square centimeter.
  • The process uses advanced tools to planarize the wafer surface and allows hermetic bonding SiO2/Cu at low temperatures (300°C).
  • Technology is jointly developed by Invensas and IZM ASSID & partners

wolf 2

Also of interest was their interposer roadmap which included not only TSV but also integrated passives, embedded chips and fluid cooling channels down the road.

Gen 1 Interposer = TSV, multi layer redistribution(RDL)

Gen 2 Interposer = + integrated passive devices

Gen 3 Interposer = + embedded active devices and/or MEMS

Gen 4 Interposer = + integrated optical & electrical interconnects

Gen 5 Interposer = + active cooling (e.g. fluid channels)

Groothuis – Samtec

Steve Groothuis discussed the use of glass interposers. Samtec acquired Triton Microtech (a glass interposer startup) last year. Their approach is to use thin fil RDL with thick film filled vias. “Samtec Microelectronics will be processing borosilicate glass, fused silica, quartz, zirconia, and sapphire wafers and eventually panels for cost and scaling.”

While they acknowledge that the glass interposer platform has not become mainstream yet, they contend that glass interposers are a strong candidate to be used in RF applications because of superior electrical insulation, low dielectric constant, high hermeticity, low warping, and high resistance to corrosion. Their design rules are shown below.

samtec 1

Samtec shows copper diffusion data and concludes “No diffusion of Cu into the glass –No need for a barrier layer along sidewall,” this leaves me somewhat puzzled since the last time I checked glass was SiO2 and we now Cu diffuses like a rabbit in SiO2. Maybe the expts were not run under bias?

They conclude that Samtec will work with customers in various areas of Glass Core Technology for prototyping, low-volume production, and paths to high-volume manufacturing.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 324 Intel EMIB Implementation in the Stratix MX

By Dr. Phil Garrou, Contributing Editor

At the recent IEEE ISSCC in SF, Intel discussed the implementation of their EMIB technology [Embedded Multi-die Interconnect Bridge] technology in the Altera Stratix 10 FPGA family designed to meet the needs of developing high end communications systems.

EMIB was first proposed by Mahajan and Sane in USP 8,064,224 which was filed in 2008 and issued in 2011 [link].

A nice description of the technology was given at the 2016 ECTC [link]

EMIB uses thin pieces of silicon (< 75um) containing fine pitch interconnect (~2um L/S) embedded in an organic substrate to enable dense die to die interconnect between die on the BGA like laminate substrate as shown below.

X sect


Assembly is by a combination of 55 micron micro-bumps and 100+ micron FC bumps to support up to 24 transceiver channels with 96 I/Os each. They deliver 2 Gbits/second/pin at 1.2 pJ/bit/die using a proprietary protocol. Currently, the bridge links four 28 GHz serdes to the FPGA.

Intel has shown the following process sequence for EMIB:



Altera [now Intel’s Programmable Systems Group (PSG)] will have a family of their upcoming Stratix 10 line that will include HBM DRAM 3D stacks from SK Hynix connected to the FPGA with Intel’s proprietary EMIB technology. They report up to 10x the memory bandwidth available by connecting the FPGA to off-chip memory.

The HMB2 DRAM chips themselves are 8Gb each, and they can be stacked up to 8 high, yielding an 8GB 256GB/s lane. Combine four of these stacks for a 1TB/s aggregate memory bandwidth. Power consumption is reduced because the memory is right next to the FPGA and drive strength is much smaller.

Intel 1

The parts integrate four stacks of HBM2 DRAM, each with up to four memory dice. Each stack can run to 256Gbyte/s, so four stacks give 1Tbyte/s, and there are still transceivers and I/O available for use with external components.

memory solutions

One can conceive of application areas such as HPC (high performance computing), cloud computing and data centers. So far, Intel has announced no other users of this EMIB technology which they made available as a foundry service two years ago. It will also be interesting to watch how Intel’s EMIB competes with the other “fan-out “ solutions the industry is offering.

It is also interesting that these products use HBM instead of HMC (hybrid memory cube) memory stacks that Intel developed with Micron [link]

For the latest in advanced packaging, stay linked to IFTLE…

IFTLE 323 The New DARPA Program “CHIPS”; Amkor Acquires Nanium; GE Licenses SEMCO

By Dr. Phil Garrou, Contributing Editor

CHIPSBack in the late 1970s, there was a TV show in the US called ChiPS which stood for California Highway Patrol. It was poorly written and even more poorly acted. Thank goodness that’s not what we are going to be talking about now.

The research wing of the Defense Department, otherwise known as DARPA, put out a broad agency announcement in Sept 2016 for a program called “Common Heterogeneous Integration and IP Reuse Strategies with the same acronym, CHIPS [BAA-16-62] with an anticipated funding level of ~ $70MM. Multiple award are expected. Final proposal due date was Dec 16th and the estimated start date was reported to be ~ 4 months after proposal submission. The program is being run by Dr. Dan Green in MTO (Microsystems Technology Office).

Pay attention to this program because it has the possibility of creating a paradigm shift in how electronics are done today. The goal is to lower cost and decrease turn around time for military electronics, but design flows that will be created could have major impact on the industry as a whole. As IFTLE has said in the past few weeks, with the end of Moores Law, we are searching for high impact alternatives and this just may be it.

As the BAA describes it, DARPA expects participants to “…leverage existing designs that would benefit from translation to a modular framework in order to enable reuse of captive IP, include commercial IP, or allow faster redesign and update cycles.” A key feature of CHIPS is the establishment of standard interfaces to promote the reusability and interchangeability of modular circuit functional blocks or chiplets. In the first phase of the program the community will “converge on a limited number of interface standards that are broadly useful.”

darpa 1



CHIPS consists of 3 technical areas (TA1) focused on modular digital designs; (TA2) focused on modular analog design and (TA3) focused on supporting technologies.

SoC (system on chip) technology has been driving the industry for several decades as further functions were implemented on chip. We are now looking at a reversal of this process. DARPA called it “dis-aggregation” IFTLE prefers to call it “disintegration”. Once in place it wil allow you to replace only functions that need to be upgraded and not have to redesign and remanufacture the whole SoC chip. Whatever you want to call it, it looks like exciting times are ahead and you will be sure IFTLE will keep you informed on all new CHIPS info as it becomes public.

Amkor Acquires Nanium

OSAT consolidation continues as Amkor and NANIUM have announced that they have entered into an agreement for Amkor to acquire NANIUM. NANIUM is based in Porto, Portugal, has 500+ employees and sales of ~ $40 million in 2016. Terms of the transaction were not disclosed.

“Amkor’s technology leadership, substantial resources and global presence coupled with NANIUM’s best-in-class WLFO packaging solutions will accelerate global acceptance and growth of this technology worldwide.”

The acquisition of NANIUM will strengthen Amkor’s position in the fast growing market of wafer-level packaging for smartphones, tablets and other applications. NANIUM has developed a high-yielding, reliable eWLB based WLFO technology, and has successfully ramped that technology to high volume production. NANIUM has shipped ~ 1B WLFO packages off their 300mm Wafer-Level Packaging (WLP) production line.

Adding this to their SLIM and SWIFT technologies which are moving into HVM Amkor seeks to expand the manufacturing scale and broaden the customer base for such fan out technology solutions.

GE Licenses SEMCO their Embedded Chip Packaging Technology

GE Ventures and Samsung Electro-Mechanics (SEMCO), have announced a patent license agreement where SEMCO will license GE microelectronics packaging patent portfolio, covering the fabrication of substrates embedded with electronic circuits. This patent portfolio was developed by GE Global Research and Imbera Electronics Oy (now GE Embedded Electronics Oy) as part of the GE focus in power electronics over the last decade. [link 1] They seek to provide significantly improved electrical performance (for example, reduced parasitics), increase functional density of the electronics circuits by more than a third, and can increase efficiency by over 10%.

GE Ventures has already licensed IP to TAIYO YUDEN for fabricating substrates embedded with electronic circuits in late 2014. “TAIYO YUDEN and GE are working towards the commercialization of next-generation wirebondless, embedded electronics circuits including Si-, SiC- and GaN-based wirebondless embedded electronics circuits with the technology and the IP provided by GE Ventures. “[link 2]

GE Ventures has also licensed SHINKO ELECTRONICS their advanced embedded packaging solution for power electronics called Power Overlay (POL) to “…industrialize the packaging platform and transition POL to manufacturing for GE and others.” [link 3]

For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 322 SEMI ISS 2017: A Period of Uncertainty?

By Dr. Phil Garrou, Contributing Editor

SEMI’s annual Industry Strategy Symposium was held at its usual site, Half Moon Bay, CA a few weeks ago.

It may just be me, but it seemed like this year’s overall message was one of an industry searching. IFTLE thinks the end of scaling and the public indications that 450mm does not appear to be moving forward has left the industry wandering a bit. Yes, there is excitement over IoT, but the exact way that this will play out in terms of low cost connectivity solutions and the inherent security dangers are not yet clear. For an industry that for the past few decades has had everything laid out on roadmaps this may be a bit disconcerting, but to IFTLE it is now significantly more exciting because the future is not as clear.

Is the following the semiconductor roadmap for the future?


With that said, here are some of the highlights of 2017 ISS from IFTLE perspective.

Linx Consulting

Corbett of Linx Consulting looked at the state of the wafer fab materials segment. They indicated that the total market for semiconductor materials in 2015 was $18.5B with most of the top players being in the wafer and gas businesses.

linx 1

The top 11 supplies have ~$12B sales. Removing the wafer suppliers leaves the following top 10 suppliers with categories of materials broken out as follows.

linx 2


As IFTLE said many years ago, consolidation in the semiconductor industry would lead to similar consolidation of their suppliers (materials and equipment). Linx presented the following materials merger list.

linx 3

International Business Strategies (IBS)

Our old friends at IBS note that:

- Apple semiconductor value in 2016 will be $9.6B

- Apple is driving advanced features including move to 10 and 7nm

- Smaller features will continue to give lower power and higher performance but now at a cost premium

- Chip scale packaging will enjoy significant growth

- 3D NAND will show high growth

- smartphones will continue to lead demand at least through 2025

- Growth of IoT will accelerate after connectivity to the cloud becomes very low cost and business models are established for monetizing value of data

Specific areas of high growth are shown below:


Western Digital / Sandisk

Chen presented an interesting history of NAND and concluded that this new conversion of 2D NAND to 3D NAND is more complex than past 2D to 2D conversions and will generate a period of limited cost reduction in the industry. In the past, 2D to 2D scaling transitions took 4-5 quarters but now 2 to 3D is expected to take 14 to 16 quarters!

WD 1

GlobalFoundries (GF)

Patton of GlobalFoundries sees 5G as disruptive technology, which will transform today’s communication architecture.

GF 1

Patton also pointed to packaging as the alternative to silicon scaling (readers certainly know that IFTLE agrees).

GF 2

For all the latest in Advanced Microelectronic Packaging, stay linked to IFTLE…

IFTLE 321 IMAPS 3D ASIP Part 4: SPIL Fan-Out Options; BESI Thermo-compression Bonding Options

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the IMAPS 3D ASIP Conference from this past December.


Albert Lan discussed Fan-out from the perspective of SPIL.

Lan showed a nice cartoon depiction of the fan out options of die first, die last and face up and face down as shown below.


Of special interest is their fan out SiP with metal lid to partition EMI. The FO-SiP requires excellent control of the compression molding process.


This will allow elimination of substrate and thus thinner packages with better electrical performance as shown below.

Their warpage “adjustment” technique is also of intrest as shown below.



Hugo Pristauz of Besi described some essentials of thermal compression bonding (TCB).

Pristauz contends that TCB is used when confronted with issues of warpage, ultra fine pitch and / or thermal stress. He points out that there are actually 3 types of TCB processes as shown below.

Besi 1


As we have detailed on IFTLE previously [see IFTLE 108 2012 ECTC 2: NCF, WUF, MUF for tight pitch Assembly], NCF appears to be the TCB process of the future.

Current technology is capable of 10um pitch assembly (C2W face up) which means 2um@3s accuracy. Any attempts to move to 1um pitch would require 200nm@3s accuracy.

A significant issue is maintaining positional accuracy and co-planarity while ramping from cold to hot. Thermal compensation needs to be identified by the bonder (automatically) and recalled from memory during bond control.


Thomas Urhman of EVG discussed technologies for high performance and high bandwidth Applications.

The interesting slide below examines use of the various debonding techniques vs applications. The debonding techniques use heat, force and light respectively to induce separation from the carrier support.



Hybrid bonding, as originally developed by Ziptronix, and as being adopted by Sony for image sensor 3D stacking, requires plasma activation of the surface and tight control of the CMP process. Excess Cu dishing can ruin the bonding. Currently processes using 3-5um pad size at 6-10um pitch are available.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 320 3D ASIP: Amkor Multi Die Packaging; Brewer‘s New Temp Bonding Sys

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the IMAPS 3D ASIP Conference 2016.


Mike Kelly of Amkor updated their status on 2.5 and 3D multi die packaging.

amkor 1

High density solutions on 2.5D interposer technology are focused on data center, networking, HPC and military.

Amkors 2.5D production readiness:

- MEOL wafer thinning and backside processing

- 300mm TSV line in K4 … K5 starting Jan 2017

- SPC control

- automated wafer handling

- yield > 97.5 % (die level)

- Assembly

- production in K4 (85K parts built to date)

Yields > 98%

Comparison of Signal Routing for high density technologies:

SWIFT production readiness:

- internally qualified

- ready for small body high volume production in Q2 2017 in K5

- large body process in development

Routing capabilities are compared below: Slim > 3x SWIFT > 3X FC

amkor 2


Emilie Jolivet of Yole shared information on memory stacks. Their look at memory stack IP concludes that the area has been dominated by Samsung, Hynix, Micron/Elpida as you would expect.

yole 1


We have previously discussed the Subu Iyer CHIPS program at UCLA [ see IFTLE 301 “Are Silicon Circuit Boards in our Future?”]

As described before, the plan here is to “disintegrate” (system partition) into functional blocks. These blocks would become a standardized IP library which would be available later as reusable IP. These chiplets (or dielets – the community has not decided what to call them) would then be recombined on a high density silicon fabric to fabricate the desired module. Iyer has calculated that these small (< 3 x 3mm) chiplets would require ~ 5um L/S to interconnect them. Lot of similarities to the current. In many ways this approach is similar to the CEA Leti chiplet activity and the DARPA CHIPS program which we shall look at soon.


Brewer Science

When you think about temporary bonding you certainly think of Brewer Science who has been developing products for this technology area for over a decade.

brewer 1

Through the years they have developed products for several potential debonding schemes:

brewer 2

Their latest development is a two part system called “thermo+ cure” bonding where a thermoplastic layer (~ 2um) first encapsulates the device features followed by a curable layer (~60um; 150-200 °C). Debonding, occurs at the thermoplastic / cured layer interface as shown below. No part of the structure, after curing, can flow during backside processing.

brewer 3

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 319 Mike Ma to Amkor; 3D ASIP Part 2: Image Sensing - Sony, Tessera, SMIC

By Dr. Phil Garrou, Contributing Editor

Ma to Amkor

Mike MaThis week, I can announce that Dr. Mike Ma, with 23 years in the microelectronics industry, has moved from SPIL to Amkor as Taiwan Country Manager. Mike served as Vice President of Corporate R&D and Spokesperson at SPIL. Mike holds M.S. in Materials Engineering from Northeastern Univ and PhD in Material Science and Engineering from North Carolina State Univ.

It’s great to see someone who has maintained his keen interest and knowledge in technology attain such a lofty position. Many of you might remember Mike during his earlier days at UMC.

We all know that when consolidation occurs like the ASE – SPIL merger (I know legally this is not being called a merger, but you also know IFTLE always calls a spade a spade) savings are achieved by staff reduction, especially at the higher levels – redundancy they call it. In this case IFTLE is confident that my friends at ASE have made a major mistake letting Mike leave. IFTLE message to Amkor – good pick up!

CMOS Imaging at 3D ASIP 

This year’s 3D ASIP put a special emphasis on CMOS image sensing.

It was the fall of 2007 when Toshiba first announced the commercialization of TSV in a CMOS image sensor (CIS). [see IFTLE 89 “Advances in CMOS Image Sensing”]

In 2012 Sony announced that it was separating the pixel section (containing the back-illuminated structure pixels) from chips containing the circuit section for signal processing, and oxide bonding the layers and then connecting them with TSV. [see IFTLE 172 “Sony TSV Stacked CMOS Image Sensors Finally Arrive in 2013”]

Seperation of pixels from circuits using oxide bonding and TSV

Seperation of pixels from circuits using oxide bonding and TSV

Earlier this year [see IFTLE 303 “Sony Introduces Ziptronix DBI Technology in Samsung Galaxy S7”] a Chipworks teardown of the Samsung Galaxy S7 revealed the first use of the Ziptronix (now Tessera) Direct Bond interconnect (DBI) technology rather than prior oxide –oxide bonding with subsequent TSVs connecting through the oxide interface (In most circles this is referred to as “HYBRID BONDING” and does not require TSV.

sony 4

So it seems only fitting that this years 3D ASIP image sensing plenary presentation was by Tetsuo Nomoto, Sr General Mgr of Sony’s mobile imaging systems business. Sony sees several key applications for CMOS image sensor technology:

sony 2

Nomoto indicates that the next generation will include stacked DRAM chips to achieve “ 5X faster scan out and storage data, improve distortion and reduce 1/F bandwidth” and then incorporating a DSP into the stack to 3 Layered modules with customized staked DRAM will be shown at the next IEEE ISSCC.

sony 3

The audience really perked up when Nomoto indicated that Sony believes such technologies will be instrumental to furthering robotics and robotic manufacturing.

sony 5

During the Tessera presentation by Paul Enquist, they described the new “hybrid bonding process as follows:

Tessera 1

Since Sony is currently in production with 6um pitch and Tessera is currently capable of 1.6um pitch in demonstration vehicles, they feel they are close to pixel level interconnect technology.

Tessera 2

Yole reports that back side stacked and back side stacked hybrid technology will take over ~ 60% of the marked by 2021.

Yole 1

Roc Blumenthal described SMICs CMOS image sensor capabilities.


Credit where credit is due

Lastly, that great cross section of the TSMC InFO package that I used in IFTLE 218 (shown below) inadvertently had the source cropped off on insertion into the blog. Full credit should go to Prismark consultants and Bingamton Univ. for this great tear down and cross section. Further details can be found in Prismark’s Semiconductor and Packaging Report Q3 2016.


For all the latest on Advanced Packaging, stay linked to IFTLE…


IFTLE 318 2016 IMAPS 3D ASIP: The Expanding World of Fan-Out Packaging

By Dr. Phil Garrou, Contributing Editor

The 13th 3D ASIP conference was held this year under the umbrella of IMAPS. This year’s meeting was chaired by Alan Huffman (Micross), Mark Scannell (CEA Leti) and Mitsumasa Koyanagi (Tohoku Univ) . I remained on board to help with the program organization and to transition the conference to IMAPS.

(L to R) Scannell, Koyonagi, Garrou, Huffman

(L to R) Scannell, Koyonagi, Garrou, Huffman

We’ll first take a look at the “Advances in Fan-out Packaging” course by Beth Keser of Qualcomm (see recent changes below) and next week begin with plenary lectures provided by Tetsuo Nomoto of Sony, Jean Michailos of ST Micro, Bill Chen of ASE and Subu Iyer of UCLA and then other key presentations.

(L to R) Keser, Nomoto, Michailos, Chen and Iyer

(L to R) Keser, Nomoto, Michailos, Chen and Iyer

Advances in Fan-out Packaging

Who better to teach the fan-out packaging course than the co-inventor of RCP while at Freescale. 20 years ago Beth was coating BCB wafers for Ted Tessier at Motorola, today she is the go to person for fan out packaging in the world. For those keeping track of such things, reports are that Beth has just become Director of Packaging at iCDG at Intel in Munich. This is the mobile business they bought from Infineon a few years ago that designs devices for mobile phones. You’ll remember them as the inventors of eWLB fan out packaging!

I won’t give away too much of her course since many of you have not yet seen the live presentation, which I recommend you all do to gain a complete understanding of what this technology is all about.

Lets start by offering up the IFTLE comment that I have used many times “ALL PACKAGES ARE FAN OUT EXCEPT FAN IN WLP” meaning lead frame packages, BGAs ect are all fan out.

By now we are all used to the FO-WLP process flow developed for the Infineon eWLB as shown below. With the proliferation of reconstituted, mold compound based FO-WLP, such processes have become known as face down, chips first.

keser 1

Reconstituted Fan-out has really taken off recently as it has been developed for multi-die , i.e SiP applications and PoP (package-on-package) applications. It has also developed capabilities to achieve much higher densities in both face down and face up process flows. For PoP applications Keser point out that it:

- eliminates warpage and co-planarity issues since there is no substrate

- offers PoP height reduction

- eliminates stress on the die from bump interconnect (maybe but there is still stress – see InFO X-sect below)

Second generation products have been coming out in rapid progression but Keser cautions that only the InFO is currently available. - Xilinx / SPIL “SLIT” [IFTLE 215]

- DECA “M series” [IFTLE 124, 175, 267]

- TSMC “InFO” [IFTLE 283, 305, 311]

- Amkor “SWIFT and SLIM” [IFTLE 243, 309]

- ASE [IFTLE 22, 269]

I will not go over all of these, but have given you links back to previous discussions in IFTLE

Of interest continues to be the upcoming ASE merger with SPIL and their announced investment to scale up the DECA FO-WLP technology [IFTLE 292].

I have commented in IFTLE 292 that DECA and InFO appear to be very similar technologies by polishing the surface during pillar expose step to produce a very flat surface for the RDL fabrication. Keser reports that TSMC is in production with 5/5 (L/S). Many of the speakers are showing InFO cross sections taken from analysis of the Apple A10 (TSMC has still not published process flow or cross section) I have included it below for those readers who have not seen it yet. This is a PoP package with memory on the top (side by side to thin the package down) and the processor below. Note the overall bow in the structure!

Keser 2

In short, “Fan-out packaging” is certainly expanding its technology capabilities and appears to be capable of taking significant package market share in the future.

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 317 IEEE 3DIC Part 2: 3D Processing at Tohoku Univ & Extreme Thinning Options for Vias Last Pkging

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the IEEE 3DIC Conference.

Tohoku Univ

Koyanagi and co-workers at Tohoku Univ studied the use of Ti as a 3D TSV barrier layer.

Cu was substituted in the early 2000s for Al interconnect wiring which no longer meet the resistivity requirements in the aggressively scaled technology nodes. Cu, which has low electrical resistivity has proved itself as a potential interconnect material, only if necessary barrier layers are in place.

The most serious concern with Cu as interconnect material is the formation of midgap defects in active Si, since it diffuses fast into the Si. Owing to this, the minority carrier life time is reduced several orders even at 200 °C. Moreover during this diffusion process since Cu travels through SiO2, the insulation nature of SiO2 is degraded which can result in premature dielectric breakdown leading to device failure. The well known method to prevent Cu diffusing into SiO2 and then in Si is to sandwich an amorphous metal layer between the Cu and SiO2. Required properties of a good barrier layer are low internal film stress, high thermal stability and low resistivity. Metals with high melting points are known to have larger activation energy for the diffusion to take place.

Although Ta is best suited as a barrier material based on melting point, Ta has more integrated film stress than Ti film, i.e. a 200 nm-thick sputtered Ta film possesses internal stress of 1.4 GPa, whereas the stress in a similar thickness Ti film is 0.8 GPa . Internal stress is the main cause for the delamination of sputtered Ta films. Thus Ti is a better barrier layer based on internal stress.

One way to improve the barrier performance of Ti, is to use a Ti/TiN structure as barrier layer, but TiN has a large resistivity (p~270 µ .

The Tohoku group has found a simple method to improve the barrier ability of Ti layer is to anneal the TSV structures in vacuum at temperatures up to 400 °C. This results in a significant improvement in leakage current characteristics for SiO2 dielectric. TiSix has been identified at the interface between Cu and SiO2 during the sputter deposition.

Another presentation by Tohoku Univ examined the reduction of keep-out-zone in 3DIC by local stress suppression with negative-CTE filler.

The thinning of the IC chips leads to low flexural rigidity of IC chips. In addition, the CTE of the underfill material is larger than that of metal microbumps. In other words, the underfill material shrinks more compared to metal microbumps. IC chips are bent by this shrinkage after the 3D integration process. This CTE mismatch induces local bending stress in thinned Si chips, and in turn effects the MOSFET electrical performance in thinned Si chips.

In general, SiO2 or Al2O3 filler have been introduced into the underfill to reduce the CTE of underfill. High density filler is required to realize a CTE close to the value of the microbumps. However, it is difficult to use the conventional density underfill for 3D IC with fine pitch microbumps due to its high viscosity. What’s required is a low viscosity low CTE underfill.

The Tohoku group suggests a negative CTE material as the filler to suppress the local bending stress. They used manganese nitride-based negative-CTE material as filler. The CTE of this material is -45 ppm/K at the temperature from 65 °C to 100 °C.

Tohoku 1


IMEC & SPTS reported on extreme wafer thinning optimization for via-last applications.

One of the approaches for 3D-SOC W2W bonding is schematically shown below. After oxide bonding, the top wafer can then be thinned and backside via-last TSV contacts can be created to connect electrically to both the top and the bottom wafers.



Two wafer thinning approaches were investigated targeting a 5μm top wafer Si final thickness:

  1. A) A combination of grinding to 25μm followed by an extensive 20μm Si CMP step
  2. B) a combination of grinding to 50μm followed by a short Si CMP step (1μm Si removal) and 44μm Si dry etch process based on a NIR end point detection system performed in an SPTS Rapier XE system.

They conclude that the safest approach combines grinding and a fast Si dry etch which, combined with an in-situ end point detection, enable a very precise and stable etch stop process at the desired

thickness. Moreover, a cost model has shown that this approach is 50% more cost effective as compared to an integration flow that would involve a long and expensive Si CMP step.


For those who havn’t seen it, Amkor has announced that they have completed product qualification of their Silicon Wafer Integrated Fan-Out Technology (SWIFT) WLFO technology for mobile, networking and SiP applications. SWIFT incorporates an “RDL first” process that allows SWIFT wafers to be built and yielded ahead of the assembly process. SWIFT is targeted for production in the second half of 2017 at K5 in Incheon, South Korea.


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