Thursday, Nov 7, 2013
Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and inspection. Smaller defects must be detected and analyzed on an increasingly diverse set of materials. Chip makers are looking for better wafer edge inspection techniques, higher resolution metrology tools, 450mm-capability and new compositional analysis solutions. Experts will describe new approaches for next generation metrology and inspection, including measurements of CDs, stress, film thickness and non-visual defects.
-Mike Lercel, Senior Director for Nanodefectivity and Metrology at SEMTECH
-Alain Diebold, Executive Director at the Center for Nanoscale Metrology SUNY College of Nanoscale Science and Engineering
Moderated by Pete Singer, Editorial Director
Mark your calendars! Registration coming soon.