Intel and IBM to lay out 14nm FinFET strategies on competing substrates at IEDM 2014

The development of increasingly sophisticated and energy-efficient CMOS technology for mobile, client and cloud computing depends on a continuing stream of advances in the process technologies with which the complex integrated circuits are built. Among the most promising chip technologies are transistors called FinFETs, which have attracted significant R&D investment and have begun to appear in commercial products.

But the technology is complex and the path forward isn’t settled, and in two late-news papers to be given at this December’s IEEE International Electron Devices Meeting (IEDM), Intel and IBM will present dueling approaches to the development of FinFET technology for the 14nm technology node, the semiconductor industry’s next big hurdle.

The IEDM is the forum where top technical experts in micro- and nanoelectronics gather to disclose, discuss and debate breakthrough technologies in the field. The 60th annual IEDM will be held at the Hilton San Francisco Union Square Hotel from December 15-17, 2014, preceded by day-long short courses on Sunday, Dec. 14 and a program of 90-minute tutorials on Saturday, Dec. 13.

All modern transistors have a channel to conduct electricity and one or more gates to turn the current on and off. FinFETs have long, thin fin-like channels (hence the name) surrounded by multiple gates. This design leads to greater performance and enhanced energy efficiency. Both Intel and IBM will present fully integrated 14nm FinFET technologies at the IEDM.

Intel, which began using FinFET transistors commercially in its “Ivy Bridge” and “Haswell” processors at the 22nm node, will detail the second generation of that technology.[i] Made on a standard bulk silicon substrate, the new “Broadwell” 14nm technology has been released commercially and is in production as part of Intel’s latest family of microprocessors.

Among the technical features Intel will discuss at the IEDM are: a novel doping technique to prevent current leakage under the fins and to maintain very low doped fins, resulting in improvement in variation; two levels of air-gap-insulated interconnects (electrical connections) at ultra-narrow 80 and 160nm minimum pitches, yielding a 17% reduction in capacitance delays; eight layers of 52nm pitch interconnects embedded in low-k dielectrics; an embedded 140Mb SRAM memory with a tiny cell size of 0.0588µm2; and saturated drive currents significantly higher than for Intel’s 22nm first-generation FinFETs (improvements of 15% and 41% for NMOS and PMOS transistors, respectively). The transistors operate with a supply voltage of only 0.7 Volts.

The researchers also will discuss how aggressive design rules enabled the production of very high aspect ratio rectangular fins (8nm wide and 42nm high) at unprecedented levels of uniformity.

IBM, meanwhile, will describe a very different approach to 14nm FinFET transistors.[ii] The IBM devices are made not from a standard bulk silicon substrate but from an insulating substrate known as SOI, a more expensive material but one which simplifies manufacturing in terms of device isolation. These devices are more than 35% faster than IBM’s 22nm planar (i.e. standard, non-FinFET) transistors, with an operating voltage of just 0.8 volts.

The IBM technology features what may be the smallest, densest embedded DRAM memory ever demonstrated (a cell size of just 0.0174µm2) for high-speed performance in a fully integrated process flow. IBM also designed an elegant way to make the technology suitable for both low-power and high-speed applications, using a unique dual-workfunction process that optimizes the threshold voltages of both NMOS and PMOS transistors without any mobility degradation in the channel.

Because the technology is envisioned for use in system-on-a-chip (SoC) applications ranging from video game consoles to enterprise-level corporate data centers, the IBM design also features a record 15 levels of copper interconnect to give circuit designers more freedom that ever before to distribute power and clock signals efficiently across an entire SoC chip, which may be as large as 600mm2.

Making transistors smaller, or scaling them according to Moore’s Law, is what has traditionally driven exponential progress in nanoelectronics and information technology. With today’s nanoscale-sized devices that has become difficult and expensive, which is why new transistor architectures such as FinFETs have become so appealing.

[i] Paper #3.7, “A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588µm2 SRAM Cell Size,” S. Natarajan et al, Intel

[ii]  Paper #3.8, “High Performance 14nm SOI FinFET CMOS Technology with 0.0174µm2 Embedded DRAM and 15 Levels of Cu Metallization,” C.-H. Lin et al, IBM


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2 thoughts on “Intel and IBM to lay out 14nm FinFET strategies on competing substrates at IEDM 2014

  1. Sang Kim

    Sang Kim
    Moore’s Law is based on the planer bulk silicon technology, and has ended at the 28nm planer bulk silicon technology node because of unable to suppress transistor leakage current at 22nm node. That is why Intel invented and developed the FinFETs at 22nm node that has a trapezoidal vertical fin structure being able to suppress leakage current and scalable to the end of the roadmap or 4nm node. Intel’s 14nm FinFETs are in volume manufactured for almost two years while IBM, GF and Samsung are not volume manufacturing FinFETs
    at any technology yet. It appears that one of the major differences between Intel’s FinFETs and IBM FinFETs to be built is that Intel FinFETs are built on a bulk silicon while IBM FinFETs are to be built on a thin SOI wafer. The SOI wafers are more costly as pointed out. Furthermore, a SOI based FinFETs are completely surrounded by top gate oxide, SOI oxide at the bottom and isolations at the sides. As a result, self-heating can occur during the transistor operation, resulting in detrimental transistor performance and reliability. Furthermore, holes as a result of hot carrier generation due to the high drain field likely trapped all at the SOI-bottom oxide interface adversely impacting transistor reliability. The other critical issue with SOI approach is that how thin un-doped SOI channel thickness is required for 14nm FinFETs, 4-5nm? How a 4-5nm thin SOI channel layer can be controlled uniformly and reliably across 12 inch wafers in a manufacturing line? How to prevent DIBL(drain field induced barrier lowering) at the source in the un-doped SOI channel? A significant mobility degradation will also occur in such an ultra thin SOI channel layer.

  2. AK

    Dear Sang Kim,

    Moore’s law did not end at 28nm because of leakage. Moore’s law is about cost per transistor, not leakage, performance, or power. You may argue that Dennard’s scaling theory ended at 28/32nm, but that’s only correct for Intel that swithced to FinFET at 22nm. Foundry stayed at bulk for 20nm and that’s what powering the latest chips from Apple and Qualcomm. Nothing is fundamentally wrong with a bulk technology.

    The IBM FinFET is a FinFET not planar FDSOI. So, it does not require ultra thin SOI wafers. The thickness of the Si layer is equal to the target fin height — say 35nm. Either SOI or bulk FinFET need the fin to be narrow, and I don’t see a big difference between fin thickness (not height) between the two.


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