Transistors made from nanowires are seen as a promising way to extend scaling beyond what FinFET and fully depleted SOI CMOS technologies can offer. A paper from CEA-LETI will describe the successful integration of dual channels (silicon and SiGe) in high-performance CMOS nanowire devices which outperform state-of-the-art SOI nanowires. The devices feature uniaxially compressively strained SiGe PFETs with a gate shaped like the Greek letter omega for tight control of electrostatics in the channel. They are co-integrated with silicon NFETs in a fully CMOS SOI-compatible process. Device dimensions are aggressively scaled to sub-15nm gate lengths, and nanowire widths are as narrow as 7 nm. Ring oscillators (test circuits) with 80 stages were built that demonstrated a 50% reduction in delay versus silicon-based counterparts, leading the researchers to argue that a dual-channel approach to nanowire-based technology is promising.
The images in the top row are transmission electron microscope (TEM) images and the ones in the bottom row are EDX (X-ray) maps of omega-gate CMOS nanowire transistors, with a diameter of 12nm and gate length of 15nm. The NFETs have a silicon channel while the PFETs have a SiGe channel. The germanium (Ge) content is estimated to be 30%.
(Paper #16.2, “Dual-Channel CMOS Co-Integration with Si NFET and Strained-SiGe PFET in Nanowire Device Architecture Featuring Sub-15nm Gate Length,” P. Nguyen et al, CEA-LETI)