2015 IEDM Slide 1: DRAMs Poised for 20nm and Below

1. DRAMs Poised for 20nm and Below
Category: Memories
Paper 26.5 - 20nm DRAM: A New Beginning of Another Revolution; Jemin Park et al, Samsung

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Further advancement in dynamic random access memories (DRAMs) has all but been given up for dead time and time again, as scaling them gets more difficult and as alternative memory technology options proliferate. Now that leading-edge technology is at 20nm and below that day might finally seem to be at hand, but designers keep coming up with new tricks to extend their usefulness. The trend will continue at the IEDM when Samsung researchers describe clever techniques they used to wring substantial performance improvements out of state-of-the-art 20nm DRAMs with no need for expensive and as-yet unproven fabrication techniques like EUV lithography. One key improvement is a honeycomb cell structure that effectively increases cell pitch by 7.5%, leading to a 57% increase in cell capacitance for improved data retention. Another is an air-gap spacer arrangement that achieves a 34% reduction in bitline capacitance for faster operation. The researchers say these techniques will be key enablers for DRAMs for the 20nm node and beyond.

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