2015 IEDM Slide 4: III-V Nanowire CMOS on Silicon

4. III-V Nanowire CMOS on Silicon
Category: Alternatives to Silicon
Paper 15.4 - Gate-All-Around CMOS (InAs n-FET and GaSb p-FET) Based on Vertically-Stacked Nanowires on a Si Platform, Enabled by Extremely-Thin Buffer Layer Technology and Common Gate Stack and Contact Modules; Kian-Hui Goh et al, National University of Singapore/Nanyang Technological University

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High electron-mobility III-V semiconductors have been intensely researched as alternative channel materials for sub-7 nm technology nodes, but one of the main stumbling blocks is how to integrate them monolithically and cost-effectively with traditional CMOS silicon technology. A team led by National University of Singapore will describe the first use of vertically stacked III-V nanowires to do so. The key was an extremely thin (sub-150nm) high-quality GaSb buffer layer on silicon. On top of it, the researchers built multi-gate InAs nFETs and GaSb pFETs from stacked InAs or GaSb nanowires, respectively. The fabrication technique employed multiple common modules such as gate stack and contact processes. Good subthreshold slope of 126 mV/decade and DIBL of 285 mV/V were obtained for the InAs nFET with a 20nm channel length. Meanwhile, the lowest reported subthreshold slope of 188 mV/decade and the highest reported Ion/Ioff ratio of 3.5 were demonstrated for the GaSb pFET, which had a channel length of 500nm. The technology may be suitable for future high-performance and low-power logic applications.


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