BY TOM QUAN, Deputy Director, TSMC
The Prophets of Doom greet every new process node with a chorus of dire warnings about the end of scaling, catastrophic thermal effects, parasitics run amok and . . . you know the rest. The fact that they have been wrong for decades has not diminished their enthusiasm for criticism, and we should expect to hear from them again with the move to 10nm design.
Like any advanced technology transition, 10nm will be challenging, but we need it to happen. Design and process innovation march hand in hand to fuel the remarkable progress of the worldwide electronics industry, clearly demonstrated by the evolution of mobile phones since their introduction (FIGURE 1).
Each generation gets harder. There are two different sets of challenges included with a new process node: the process technology issues and the ecosystem issues.
Process technology challenges include:
- Lithography: continue to scale to 193nm immersion
- Device: continue to deliver 25-30% speed gain at the same or reduced power
- Interconnect: address escalating parasitics
- Production: ramp volume in time to meet end-customer demand
- Integration of multiple technologies for future systems
Ecosystem challenges include:
- Quality: optimize design trade-off to best utilize technology
- Complexity: tackle rising technology and design complexity
- Schedule: shortened development runway to meet product market window
Adding to these challenges at 10nm is that things get a whole lot more expensive, threatening to upset the traditional benefits of Moore’s Law. We can overcome the technical hurdles but at what cost? At 10nm and below from a process point of view, we can provide PPA improvements but development costs will be high so we need to find the best solutions. Every penny will count at 7nm and 10nm.
Design used to be fairly straightforward for a given technology. The best local optimum was also the best overall optimum: shortest wire length is best; best gate-density equates to the best area scaling; designing on best technology results in the best cost. But these rules no longer apply. For example, sub-10nm issues test conventional wisdom since globalized effects can no longer be resolved by localized approaches. Everything has to be co-optimized; to keep PPA scaling at 10nm and beyond requires tighter integration between process, design, EDA and IP. Increasing complexity and shrinking development runways call for a new design ecosystem collaboration model (FIGURE 2).
Our research and pathfinding teams have been working on disruptive new transistor architectures and materials beyond HKMG and FinFET to enable further energy efficient CMOS scaling. In the future, gate-all-around or narrow wire transistor could be the ultimate device structure. High mobility Ge and III-V channel materials are promising for 0.5V and below operations.
Scaling in the sub-10nm era is more challenging and costly than ever, presenting real opportunities for out-of-box thinking and approaches within the design ecosystem. There is also great promise in wafer-level integration of multiple technologies, paving the way for future systems beyond SoC.
A strong, comprehensive and collaborative ecosystem is the best way to unleash our collective power to turn the designer’s vision into reality.